PLS101

Philips Semiconductors Programmable Logic Devices Product specification Programmable logic arrays (16 × 48 × 8) PLS100/PLS101 DESCRIPTION The PLS100 (3-State) and PLS101 (Open Collector) are bipolar, fuse Programmable Logic Arrays (PLAs). Each device utilizes the standard AND/OR/Invert architecture to directly implement custom sum of product equations. Each device consists of 16 dedicated inputs and 8 dedicated outputs. Each output is capable of being actively controlled by any or all of the 48 product terms. The True, Complement, or Don’t Care condition of each of the 16 inputs and be ANDed together to comprise one P-term. All 48 P-terms can be selectively ORed to each output. The PLS100 and PLS101 are fully TTL compatible, and chip enable control for expansion of input variables and output inhibit. They feature either Open Collector or 3-State outputs for ease of expansion of product terms and application in bus-organized systems. Order codes are listed in the Ordering Information Table. FEATURES Field-programmable (Ni-Cr link) Input variables: 16 Output functions: 8 Product terms: 48 I/O propagation delay: 50ns (max.) Power dissipation: 600mW (typ.) Input loading: –100µA (max.) Chip Enable input Output option: – PLS100: 3-State – PLS101: Open-Collector PIN CONFIGURATIONS N Package FE* 1 I7 2 I6 3 I5 4 I4 5 I3 6 I2 7 I1 8 I0 9 F7 10 F6 11 F5 12 F4 13 GND 14 28 VCC 27 I8 26 I9 25 I10 24 I11 23 I12 22 I13 21 I14 20 I15 19 CE 18 F0 17 F1 16 F2 15 F3 ...