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HY57V561620 Dataheets PDF



Part Number HY57V561620
Manufacturers Hynix Semiconductor
Logo Hynix Semiconductor
Description 4Banks x 4M x 16Bit Synchronous DRAM
Datasheet HY57V561620 DatasheetHY57V561620 Datasheet (PDF)

HY57V561620(L)T 4Banks x 4M x 16Bit Synchronous DRAM DESCRIPTION The HY57V561620T is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V561620 is organized as 4 banks of 4,194,304x16. The HY57V561620T is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelin.

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HY57V561620(L)T 4Banks x 4M x 16Bit Synchronous DRAM DESCRIPTION The HY57V561620T is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V561620 is organized as 4 banks of 4,194,304x16. The HY57V561620T is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline ( CAS latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.) FEATURES • • • Single 3.3V ± 0.3V power supply All device pins are compatible with LVTTL interface JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch All inputs and outputs referenced to positive edge of system clock Data mask function by UDQM and LDQM Internal four banks operation • • • • Auto refresh and self refresh 8192 refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4, 8 and Full Page for Sequential Burst • - 1, 2, 4 and 8 for Interleave Burst Programmable CAS Latency ; 2, 3 Clocks • • ORDERING INFORMATION Part No. HY57V561620T-HP HY57V561620T-H HY57V561620T-8 HY57V561620T-P HY57V561620T-S HY57V561620LT-HP HY57V561620LT-H HY57V561620LT-8 HY57V561620LT-P HY57V561620LT-S Clock Frequency 133MHz 133MHz 125MHz 100MHz 100MHz 133MHz 133MHz 125MHz 100MHz 100MHz Power Organization Interface Package Normal 4Banks x 4Mbits x16 LVTTL 400mil 54pin TSOP II Lower Power This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Revision 1.8 / Apr.01 HY57V561620(L)T PIN CONFIGURATION VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM /WE /CAS /RAS /CS BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS NC UDQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 VSS 54pin TSOP II 400mil x 875mil 0.8mm pin pitch PIN DESCRIPTION PIN CLK Clock PIN NAME DESCRIPTION The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Enables or disables all.


HM5164165F HY57V561620 HY57V561620L


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