CY3128

8 m o .c U 4 t e e Features h S a at .D w w w CY3128 Warp Professional™ CPLD Software Support for all Cypress Programmable Logic Devices — PSI™ (Programmable Serial Interface™) — Delta39K™ CPLDs — Quantum38K™ CPLDs — Ultra37000™ CPLDs — FLASH370i™ CPLDs — MAX340™ CPLDs — Industry standard PLDs (16V8, 20V8, 22V10) VHDL and Verilog timing model output for use with third-party simulators Active-HDL™ Sim Release 4.1 timing simulation from Aldec — Graphical waveform simulator — Graphical entry and modification of stimulus waveforms — Ability to compare waveforms and highlight differences before and after a design change — Ability to probe internal nodes — Display of inputs, outputs, and high impedance (Z) signals in different colors — Automatic clock and pulse creation — Support for buses — Up to 5 ms simulation time Architecture Explorer analysis tool and Dynamic Timing Analysis for PSI, Delta39K and Quantum38K devices: — Graphical representation of exactly how your design will be implemented on your specific target device — Zoom from the device level down to the macrocell level — Determine the timing for any path and view that path on a graphical representation of the chip Static Timing Report for all devices UltraISR Programming Cable Delta39K\Ultra37000 prototype board with a CY37256V 160-pin TQFP device and a CY39100V 208-pin PQFP device[1] On-line documentation and help VHDL (IEEE 1076 and 1164) and Verilog (IEEE 1364) high-level language compilers with...