ICS333

ICS333 QTClock Triple Output Clock Description The ICS333 is a low cost frequency generator that is factory programmable. Using analog/digital Phase-Locked-Loop (PLL) techniques, the device uses a standard fundamental mode, inexpensive crystal or clock input to produce three output clocks. One or more of the outputs can be programmed to implement spread spectrum for EMI reductions. The device also has a power down feature that tri-states the clock outputs and turns off the PLL when the PDTS pin is taken low. This datasheet is to be used with the one-page programming information for the complete specification on the device. Features 8 pin SOIC package Zero ppm synthesis error Input crystal frequency from 5 to 27 MHz Input clock frequency from 3 to 50 MHz Three output clocks Spread spectrum capability for low EMI Output clock frequencies up to 200 MHz Duty cycle of 45/55 3.3 V operating voltage (consult ICS for 5V) Advanced, low power CMOS process For one output clock (lowest jitter), use the ICS331. For two output clocks, see the ICS332. For more than three outputs, see the ICS355 or ICS388. Block Diagram Crystal or Clock Input X 1/IC LK X2 w w w O TP ROM w ith P LL D ivider V alues .D t a S a e h t e U 4 .c m o P LL C lock S ynthesis and Control C ircuitry C LK 1 C LK 2 C LK 3 C rystal O scillator P D TS (all outputs and P LL) MDS 333 D 1 Revision 020102 Integrated Circuit Systems, Inc. q 525 Race Street, San Jose, CA 95126 q tel ...