CXD8752Q

CXD8752Q (1/3) IL08 TIMING GENERRATOR —TOP VIEW— 36 35 34 33 32 31 30 29 28 27 26 25 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 I/O O O O O O — — I I I I I SIGNAL CAMENO BUSY CL CLD CKO GND VCC TRGM TRIG PS SMD1 OSCI PIN NO. 13 14 15 16 17 18 19 20 21 22 23 24 I/O I/O I I I I — — O O O O O SIGNAL OSCO SMD2 STRB DCLK DATA GND VCC RG w w w t a .D S a H1 H2 PIN NO. 25 26 27 28 29 30 31 32 33 34 35 36 e h O O O I I — — O O O O O U 4 t e SIGNAL .c m o SIGNAL PBLK ID WEN VD60 GRST GND VCC STDBY I ACT MCENI VD HD 1 2 3 4 5 6 7 8 9 10 11 12 I/O PIN NO. 37 38 39 40 41 42 43 44 45 46 47 48 I/O O O O O I — — I I I I I V2 V1 SG TSTMD WM VCC GND SUB V3 SHP SHD RS CPDM CPOB www.DataSheet4U.com CXD8752Q (2/3) INPUTS DATA DCLK GRST HD I ACT MCENI OSCI PS SMD1, SMD2 STDBY STRB TRGM TRIG TSTMD VD WM OUTPUTS BUSY CAMENO CKO CL CLD : : : : : : : : : : : : : : : : SERIAL INTERFACE DATA SERIAL INTERFACE CLOCK RESET HORIZONTAL DRIVE PULS MC ISO ACT CPU ENABLE OSCILLATOR SHUTTER SPEED PARALLEL OR SERIAL SHUTTER MODE STANDBY SERIAL INTERFACE STROBE TRIGGER MODE EXT TRIGGER PULSE TEST MODE VERTICAL DRIVE PULSE WRITE ENABLE MODE CPDM CPOB H1, H2 ID PBLK RG RS SG SHD SHP SUB V1 - V3 VD60 WEN : : : : : : : : : : : : : : : : : : : BUSY CAMERA ENABLE CLOCK (24.5 MHz) CLOCK (12.3 MHz) CLOCK FOR A/D CONVERTER CCD DUMMY SIGNAL CLAMP PULSE CCD OPTICAL BLACK CLAMP PULSE HORIZONTAL REGISTER CLOCK VERTICAL LINE DISCR...