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STLC2500 Dataheets PDF



Part Number STLC2500
Manufacturers ST Microelectronics
Logo ST Microelectronics
Description BLUETOOTH SINGLE CHIP
Datasheet STLC2500 DatasheetSTLC2500 Datasheet (PDF)

STLC2500 BLUETOOTH™ SINGLE CHIP PRELIMINARY DATA 1 ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ FEATURES Bluetooth™ specification compliance: V1.1 and V1.2 Ericsson Licensing Technology Baseband Core (EBC) Point-to-point, point-to-multi-point (up to 7 slaves) and scatternet capability Asynchronous Connection Oriented (ACL) logical transport link Synchronous Connection Oriented (SCO) link: 2 simultaneous SCO channels Support Pitch-Period Error Concealment (PPEC) – Improves speech quality i.

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STLC2500 BLUETOOTH™ SINGLE CHIP PRELIMINARY DATA 1 ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ FEATURES Bluetooth™ specification compliance: V1.1 and V1.2 Ericsson Licensing Technology Baseband Core (EBC) Point-to-point, point-to-multi-point (up to 7 slaves) and scatternet capability Asynchronous Connection Oriented (ACL) logical transport link Synchronous Connection Oriented (SCO) link: 2 simultaneous SCO channels Support Pitch-Period Error Concealment (PPEC) – Improves speech quality in the vicinity of interference – Improves coexistence with WLAN – Works at receiver, no Bluetooth implication Adaptive Frequency Hopping (AFH): hopping kernel, channel assessment as Master and as Slave Faster Connection: Interlaced scan for Page and Inquiry scan, first FHS without random back off, RSSI used to limit range Extended SCO (eSCO) links HW support for packet types – ACL: DM1, 3, 5 and DH1, 3, 5 – SCO: HV1, 3 and DV – eSCO: EV3, 5 Clock support – System clock input (digital or sine wave) at 13, 26, 19.2 or 38.4 MHz – LPO clock input at 3.2, 16.384, 32 or 32.768 kHz ARM7TDMI CPU – 32-bit Core – AMBA (AHB-APB) bus configuration Patch RAM capability Memory organization – On chip RAM, including provision for patches – On chip ROM, preloaded with SW up to HCI Communication interfaces – Fast UART – PCM interface – 4 programmable GPIOs – External interrupts possible through the GPIOs – Fast master I2C interface Efficient support for WLAN coexistence in collocated scenario Ciphering support up to 128 bits key Software support – Lower level stack (up to HCI) – HCI Transport Layer: H4 (including propri- Figure 1. Package TFBGA84 Table 1. Order Codes Part Number STLC2500 Package TFBGA84 ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ etary extensions) – HCI proprietary commands (e.g. peripherals control) – Single HCI command for patch/upgrade download Single power supply with internal regulators for core voltage generation Supports 1.65 to 2.85 Volts IO systems Total number of external components limited to 7 (6 decoupling capacitors and 1 filter) thanks to: – Fully integrated synthesizer (VCO and loop filter) – Integrated antenna switch – Low IF receiver Auto calibration (VCO, Filters) No need for calibration of the RF part Timer and watchdog Power class 2 compatible Ultra low power architecture with 3 different low power levels: – Sleep Mode – Deep Sleep Mode – Complete Power Down Mode Software Initiated Low Power Mode Dual Wake-up mechanism: initiated either by the Host or by the Bluetooth device Standard TFBGA-84 pins package 2 DESCRIPTION The STLC2500 is a single chip ROM-based Bluetooth solution implemented in 0.13 m ultra low power, low leakage CMOS technology for applications requiring integration up to HCI level. Patch RAM is available enabling multiple patches/upgrades. The STLC2500's main interfaces are UART for HCI transport, PCM for voice and GPIOs for control purposes. The Radio is designed for the single chip requirement and for drastic power consumption reduction. REV. 1 1/23 May 2004 This is preliminary information on a new product now in development. Details are subject to change without notice. STLC2500 3 QUICK REFERENCE DATA VDD_IO_x means VDD_IO_A, VDD_IO_B. (See also table 13 subsection Power supply.) 3.1 Absolute Maximum Ratings The Absolute Maximum Rating (AMR) corresponds to the maximum value that can be applied without leading to instantaneous or very short-term unrecoverable hard failure (destructive breakdown). Table 2. Absolute Maximum Ratings Symbol VDD_HV VDD_IO_x Vssdiff Vin Tstg Tlead Supply voltage I/O Maximum voltage difference between different types of VSS pins Input voltage of any digital pin Storage temperature Lead temperature <10s Parameter Regulator input supply voltage Min. Vss - 0.3 Vss - 0.3 -0.3 Vss - 0.3 -65 Max. 4.0 4.0 0.3 4.0 +150 +250 Unit V V V V °C °C VSS can be any VSS_xxx pin. 3.2 Operating Ranges Operating ranges define the limits for functional operation and parametric characteristics of the device. Functionality outside these limits is not implied. Table 3. Operating ranges Symbol Tamb VDD_HV VDD_IO_A VDD_IO_B Parameter Operating ambient temperature Regulator input supply voltage Supply voltage for I/O Supply voltage for I/O Min. -40 2.65(*) 1.65 1.35 2.75 Typ. Max. +85 2.85(*) 2.85(**) 2.85(**) Unit ° C V V V (*) The chip will be characterized from 2.62 [V] up to 2.9 [V]. (**) The chip will be characterized up to 2.9 [V]. 3.3 I/O specifications The I/Os comply with the EIA/JEDEC standard JESD8-B. Table 4. DC Input specification (all digital I/Os except system clock) Symbol VIL VIH Vhyst Parameter Low Level input voltage High Level input voltage Schmitt trigger hysteresis 0.65 * VDD_IO_x 0.4 0.5 0.6 Min. Typ. Max. 0.35 * VDD_IO_x Unit V V V Table 5. DC Output specification Symbol VOL VOH Parameter Low Level output voltage High Level output voltage Condition Id = X mA Id = X mA VDD_IO_x - 0.15 Min. Typ. Max. 0.15 Unit V V Note: X is the source/sink current under worst.


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