EBD52EC8AKFA-5

PRELIMINARY DATA SHEET 512MB Unbuffered DDR SDRAM DIMM EBD52EC8AKFA-5 (64M words × 72 bits, 2 Ranks) Description The EBD52EC8AKFA is 64M words × 72 bits, 2 ranks Double Data Rate (DDR) SDRAM unbuffered module, mounting 18 pieces of 256M bits DDR SDRAM sealed in TSOP package. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 2 bits prefetch-pipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. This module provides high density mounting without utilizing surface mount technology. Decoupling capacitors are mounted beside each TSOP on the module board. Features 184-pin socket type dual in line memory module (DIMM)  PCB height: 31.75mm  Lead pitch: 1.27mm 2.5V power supply Data rate: 400Mbps (max.) 2.5 V (SSTL_2 compatible) I/O Double Data Rate architecture; two data transfers per clock cycle Bi-directional, data strobe (DQS) is transmitted /received with data, to be used in capturing data at the receiver Data inputs and outputs are synchronized with DQS 4 internal banks for concurrent operation (Component) DQS is edge aligned with data for READs; center aligned with data for WRITEs Differential clock inputs (CK and /CK) DLL aligns DQ and DQS transitions with CK transitions Commands entered on each posit...