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EBD52UC8AKFA-5-E Dataheets PDF



Part Number EBD52UC8AKFA-5-E
Manufacturers Elpida Memory
Logo Elpida Memory
Description 512MB Unbuffered DDR SDRAM DIMM
Datasheet EBD52UC8AKFA-5-E DatasheetEBD52UC8AKFA-5-E Datasheet (PDF)

PRELIMINARY DATA SHEET 512MB Unbuffered DDR SDRAM DIMM EBD52UC8AKFA-5-E (64M words × 64 bits, 2 Ranks) Description The EBD52UC8AKFA is 64M words × 64 bits, 2 ranks Double Data Rate (DDR) SDRAM unbuffered module, mounting 16 pieces of 256M bits DDR SDRAM sealed in TSOP package. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 2 bits prefetch-pipelined architecture. Data strobe (DQS) both for read and write are ava.

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PRELIMINARY DATA SHEET 512MB Unbuffered DDR SDRAM DIMM EBD52UC8AKFA-5-E (64M words × 64 bits, 2 Ranks) Description The EBD52UC8AKFA is 64M words × 64 bits, 2 ranks Double Data Rate (DDR) SDRAM unbuffered module, mounting 16 pieces of 256M bits DDR SDRAM sealed in TSOP package. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 2 bits prefetch-pipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. This module provides high density mounting without utilizing surface mount technology. Decoupling capacitors are mounted beside each TSOP on the module board. Features • 184-pin socket type dual in line memory module (DIMM)  PCB height: 31.75mm  Lead pitch: 1.27mm  Lead-free • 2.5V power supply • Data rate: 400Mbps (max.) • 2.5 V (SSTL_2 compatible) I/O • Double Data Rate architecture; two data transfers per clock cycle • Bi-directional, data strobe (DQS) is transmitted /received with data, to be used in capturing data at the receiver • Data inputs and outputs are synchronized with DQS • 4 internal banks for concurrent operation (Components) • DQS is edge aligned with data for READs; center aligned with data for WRITEs • Differential clock inputs (CK and /CK) • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data referenced to both edges of DQS • Data mask (DM) for write data • Auto precharge option for each burst access • Programmable burst length: 2, 4, 8 • Programmable /CAS latency (CL): 3 • Programmable output driver strength: normal/weak • Refresh cycles: (8192 refresh cycles /64ms)  7.8µs maximum average periodic refresh interval • 2 variations of refresh  Auto refresh  Self refresh Document No. E0601E10 (Ver. 1.0) Date Published October 2004 (K) Japan URL: http://www.elpida.com Elpida Memory, Inc. 2004 EBD52UC8AKFA-5-E Ordering Information Data rate Component JEDEC speed bin Mbps (max.) (CL-tRCD-tRP) 400 DDR400B (3-3-3) DDR400C (3-4-4) Contact pad Gold Part number EBD52UC8AKFA-5B-E EBD52UC8AKFA-5C-E Package 184-pin DIMM (lead-free) Mounted devices EDD2508AKTA-5B-E EDD2508AKTA-5B/5C-E Pin Configurations Front side 1 pin 52 pin 53 pin 92 pin 93 pin Back side 144 pin 145 pin 184 pin Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Pin name VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC NC VSS DQ8 DQ9 DQS1 VDD CK1 /CK1 VSS DQ10 DQ11 CKE0 VDD DQ16 DQ17 DQS2 VSS A9 DQ18 A7 Pin No. 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Pin name NC A0 NC VSS NC BA1 DQ32 VDD DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 VDD /WE DQ41 /CAS VSS DQS5 DQ42 DQ43 VDD NC DQ48 DQ49 VSS /CK2 Pin No. 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 Pin name VSS DQ4 DQ5 VDD DM0/DQS9 DQ6 DQ7 VSS NC NC NC VDD DQ12 DQ13 DM1/DQS10 VDD DQ14 DQ15 CKE1 VDD NC DQ20 A12 VSS DQ21 A11 DM2/DQS11 VDD DQ22 Pin No. 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 Pin name VSS NC A10 NC VDD NC VSS DQ36 DQ37 VDD DM4/DQS13 DQ38 DQ39 VSS DQ44 /RAS DQ45 VDD /CS0 /CS1 DM5/DQS14 VSS DQ46 DQ47 NC VDD DQ52 DQ53 NC Preliminary Data Sheet E0601E10 (Ver. 1.0) 2 EBD52UC8AKFA-5-E Pin No. 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 Pin name VDD DQ19 A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 VSS A1 NC NC VDD Pin No. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 Pin name CK2 VDD DQS6 DQ50 DQ51 VSS VDDID DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA SCL Pin No. 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 Pin name A8 DQ23 VSS A6 DQ28 DQ29 VDD DM3/DQS12 A3 DQ30 VSS DQ31 NC NC VDD CK0 /CK0 Pin No. 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 Pin name VDD DM6/DQS15 DQ54 DQ55 VDD NC DQ60 DQ61 VSS DM7/DQS16 DQ62 DQ63 VDD SA0 SA1 SA2 VDDSPD Preliminary Data Sheet E0601E10 (Ver. 1.0) 3 EBD52UC8AKFA-5-E Pin Description Pin name A0 to A12 BA0, BA1 DQ0 to DQ63 /RAS /CAS /WE /CS0, /CS1 CKE0, CKE1 CK0 to CK2 /CK0 to /CK2 DQS0 to DQS7 DM0 to DM7/DQS9 to DQS16 SCL SDA SA0 to SA2 VDD VDDSPD VREF VSS VDDID NC Function Address input Row address Column address Data input/output Row address strobe command Column address strobe command Write enable Chip select Clock enable Clock input Differential clock input Input and output data strobe Input mask Clock input for serial PD Data input/output for serial PD Serial address input Power for internal circuit Power for serial EEPROM Input reference voltage Ground VDD identification flag No connection A0 to A12 A0 to A9 Bank select address Preliminary Data Sheet E0601E10 (Ver. 1.0) 4 EBD52UC8AKFA-5-E Serial PD Matrix Byte No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23.


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