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ICX054AK
1/3-inch CCD Image Sensor for NTSC Color Camera For the availability of this product, please contact the sales office.
Description The ICX054AK is an interline CCD solid-state image sensor suitable for NTSC 1/3-inch color video cameras. High sensitivity is achieved through the adoption of Ye, Cy, Mg and G complementary color mosaic filters and HAD (Hole-Accumulation Diode) sensors. This chip features a field period readout system, and an electronic shutter with variable chargestorage time. Features • High sensitivity (+3dB compare with ICX044BKA) and low dark current • Continuous variable-speed shutter 1/60s (Typ.), 1/100s to 1/10000s • Low smear • Excellent antiblooming characteristics • Ye, Cy, Mg and G complementary color mosaic filters on chip • Horizontal register: 5V drive • Reset gate: 5V drive Device Structure • Optical size: • Number of effective pixels: • Number of total pixels: • Interline CCD image sensor • Chip size: • Unit cell size: • Optical black: • Number of dummy bits: • Substrate material: 16 pin DIP (Plastic)
Pin 1 1
V
12 2 Pin 9 H 25
Optical black position (Top View)
1/3-inch format 510 (H) x 492 (V) approx. 250K pixels 537 (H) x 505 (V) approx. 270K pixels 6.00mm (H) x 4.96mm (V) 9.6µm (H) x 7.5µm (V) Horizontal (H) direction: Front 2 pixels, Rear 25 pixels Vertical (V) direction: Front 12 pixels, Rear 1 pixel Horizontal 16 Vertical 1 (even field only) Silicon
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E92107C66-ST
ICX054AK
VOUT
VGG
VSS
GND
Vφ2
8
7
6
5
Vφ1
Vφ 3
4
3
2
Cy
Ye Mg Ye Mg Ye G
Cy G Cy G Cy Mg
Ye Mg Ye Mg Ye G
Vertical register
G Cy G Cy Mg
Horizontal register Note) 9 10 11 12 13 14 15 16 : Photo sensor
GND
SUB
Pin Description Pin No. 1 2 3 4 5 6 7 8 Symbol Vφ4 Vφ3 Vφ2 Vφ1 GND VGG VSS VOUT
Description Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock GND Output amplifier gate bias Output amplifier source Signal output
VDD
Pin No. 9 10 11 12 13 14 15 16
Hφ1
Symbol VDD GND SUB VL RG NC Hφ1 Hφ2
Hφ 2
VL
RG
NC
Vφ4
1 Note
Block Diagram and Pin Configuration (Top View)
Description Output amplifier drain supply GND Substrate (Overflow drain) Protective transistor bias Reset gate clock
Horizontal register transfer clock Horizontal register transfer clock
Absolute Maximum Ratings Item Substrate voltage SUB – GND Supply voltage VDD, VOUT, VSS – GND VDD, VOUT, VSS – SUB Vφ1, Vφ2, Vφ3, Vφ4 – GND Vφ1, Vφ2, Vφ3, Vφ4 – SUB Ratings –0.3 to +55 –0.3 to +18 –55 to +10 –15 to +20 to +10 to +15 to +17 –17 to +17 –10 to +15 –55 to +10 –65 to +0.3 –0.3 to +30 –0.3 to +24 –0.3 to +20 –30 to +80 –10 to +60 –2– Unit V V V V V V V V V V V V V V °C °C ∗1 Remarks
Vertical clock input voltage
Voltage difference between vertical clock input pins Voltage difference between horizontal clock input pins Hφ1, Hφ2 – Vφ4 Hφ1, Hφ2, RG, VGG – GND Hφ1, Hφ2, RG, VGG – SUB VL – SUB Vφ1, Vφ2, Vφ3, Vφ4, VDD, VOUT – VL RG – VL VGG, Vss, Hφ1, Hφ2 – VL Storage temperature Operating temperature ∗1 +27V (Max.) when clock width < 10µs, clock duty factor < 0.1%.
ICX054AK
Bias Conditions Item Output amplifier drain voltage Output amplifier gate voltage Output amplifier source Substrate voltage adjustment range Fluctuation range after substrate voltage adjustment Reset gate clock voltage adjustment range Fluctuation range after reset gate clock voltage adjustment Protective transistor bias Symbol VDD VGG VSS VSUB ∆VSUB VRGL ∆VRGL VL Min. 14.55 1.75 Typ. 15.0 2.0 Max. 15.45 2.25 Unit V V ±5% V % V % ∗1 ∗1 Remarks
Grounded with 680Ω resistor 9.0 –3 1.0 –3 ∗2 18.5 +3 4.0 +3
DC Characteristics Item Output amplifier drain current Input current Input current Symbol IDD IIN1 IIN2 Min. Typ. 3 1 10 Max. Unit mA µA µA ∗3 ∗4 Remarks
∗1 Indications of substrate voltage (VSUB) · reset gate clock voltage (VRGL) setting value. The setting values of substrate voltage and reset gate clock voltage are indicated on the back of the image sensor by a special code. Adjust substrate voltage (VSUB) and reset gate clock voltage (VRGL) to the indicated voltage. Fluctuation range after adjustment is ±3%. VSUB code VRGL code one character indication one character indication ↑ ↑ VRGL code VSUB code Code and optimal setting correspond to each other as follows. 1 2 3 4 5 6 7
VRGL code Optimal setting VSUB code Optimal setting
1.0 1.5 2.0 2.5 3.0 3.5 4.0 E f G h J K L m N P Q R S T U V W X Y Z
9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 17.0 17.5 18.0 18.5
“5L” → VRGL = 3.0V VSUB = 12.0V ∗2 VL setting is the VVL voltage of the v.