WEDPN4M72V

White Electronic Designs 4Mx72 Synchronous DRAM* FEATURES            Package:  219 Plastic Ball Grid Array (PBGA), 25 x 21mm Single 3.3V ±0.3V power supply Fully Synchronous; all signals registered on positive edge of system clock cycle Internal pipelined operation; column address can be changed every clock cycle Internal banks for hiding row access/precharge Programmable Burst length 1,2,4,8 or full page 4096 refresh cycles Commercial, Industrial and Military Temperature Ranges Organized as 4M x 72 Weight: WEDPN4M72V-XBX - 2 grams typical High Frequency = 100, 125MHz WEDPN4M72V-XBX GENERAL DESCRIPTION The 32MByte (256Mb) SDRAM is a high-speed CMOS, dynamic random-access ,memory using 5 chips containing 67,108,864 bits. Each chip is internally configured as a quad-bank DRAM with a synchronous interface. Each of the chip’s 16,777,216-bit banks is organized as 4,096 rows by 256 columns by 16 bits.    60% SPACE SAVINGS Reduced part count Reduced I/O count  19% I/O Reduction w w    w Lower inductance and capacitance for low noise performance Suitable for hi-reliability applications Upgradeable to 8M x 72 density with same footprint (contact factory for information) * This product is Not Recommended for New Designs, refer to WEDPN4M72V-XB2X for new designs. Nata .D Area I/O Count T O 22.3 R The 256Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectu...