White Electronic Designs
WEDPN4M72V-XBX
4Mx72 Synchronous DRAM*
FEATURES
High Frequency = 100, 125MHz
Package:
* 219 Plastic Ball Grid Array (PBGA), 25 x 21mm
D Single 3.3V ±0.3V power supply
Fully Synchronous; all signals registered on positive
Eedge of system clock cycle
Internal pipelined operation; column address can be
Dchanged every clock cycle
Internal banks for hiding row access/precharge
N Programmable Burst length 1,2,4,8 or full page
E 4096 refresh cycles
Commercial, Industrial and Military Temperature
Ranges
M Organized as 4M x 72
Weight: WEDPN4M72V-XBX - 2 grams typical
MBENEFITS
O 60% SPACE SAVINGS
C Reduced part count
Reduced I/O count
E 19% I/O Reduction
w Lower inductance and capacitance for low noise
w Rperformance
Suitable for hi-reliability applications
w T Upgradeable to 8M x 72 density with same footprint
(contact factory for information)
.DO* This product is Not Recommended for New Designs, refer to WEDPN4M72V-XB2X
for new designs.
GENERAL DESCRIPTION
The 32MByte (256Mb) SDRAM is a high-speed CMOS,
dynamic random-access ,memory using 5 chips containing
67,108,864 bits. Each chip is internally configured as a
quad-bank DRAM with a synchronous interface. Each of
the chip’s 16,777,216-bit banks is organized as 4,096 rows
by 256 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed (BA0, BA1 select the bank; A0-
11 select the row). The address bits registered coincident
with the READ or WRITE command are used to select the
starting column location for the burst access.
The SDRAM provides for programmable READ or WRITE
burst lengths of 1, 2, 4 or 8 locations, or the full page, with
a burst terminate option. An AUTO PRECHARGE function
may be enabled to provide a self-timed row precharge that
is initiated at the end of the burst sequence.
The 256Mb SDRAM uses an internal pipelined architecture
to achieve high-speed operation. This architecture is
compatible with the 2n rule of prefetch architectures, but
it also allows the column address to be changed on every
clock cycle to achieve a high-speed, fully random access.
Precharging one bank while accessing one of the other
three banks will hide the precharge cycles and provide
seamless, high-speed, random-access operation.
Nata Discrete Approach
S 11.9 11.9 11.9 11.9
11.9
he54
e22.3 TSOP
54
TSOP
54
TSOP
54
TSOP
54
TSOP
t4UArea
5 x 265mm2 = 1328mm 2
.cI/O
oCount
5 x 54 pins = 270 pins
mWhite Electronic Designs Corp. reserves the right to change products or specifications without notice.
ACTUAL SIZE
White Electronic Designs
WEDPN4M72V-XBX
21
25
S
A
V
I
N
G
S
525mm 2
60%
219 Balls 19%
April, 2004
Rev. 15
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
