MC54HC4040A

MOTOROLA SEMICONDUCTOR TECHNICAL DATA 12-Stage Binary Ripple Counter High–Performance Silicon–Gate CMOS The MC54/74C4040A is identical in pinout to the standard CMOS MC14040. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of 12 master–slave flip–flops. The output of each flip–flop feeds the next and the frequency at each output is half of that of the preceding one. The state counter advances on the negative–going edge of the Clock input. Reset is asynchronous and active–high. State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and may have to be gated with the Clock of the HC4040A for some designs. Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 µA High Noise Immunity Characteristic of CMOS Devices In Compliance With JEDEC Standard No. 7A Requirements Chip Complexity: 398 FETs or 99.5 Equivalent Gates MC54/74HC4040A J SUFFIX CERAMIC PACKAGE CASE 620–10 1 16 16 1 N SUFFIX PLASTIC PACKAGE CASE 648–08 16 1 D SUFFIX SOIC PACKAGE CASE 751B–05 16 1 DT SUFFIX TSSOP PACKAGE CASE 948F–01 ORDERING INFORMATION LOGIC DIAGRAM 9 7 6 5 Clock 10 3 2 4 13 12 14 15 1 Reset 11 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 X Clock MC54HCXXXXAJ MC74HCXXXXAN MC74HCXXXXAD MC74HCXXXX...