KM416S1020C

KM416S1020C CMOS SDRAM 1M x 16 SDRAM 512K x 16bit x 2 Banks Synchronous DRAM LVTTL Revision 0.6 September 1998 Samsung Electronics reserves the right to change products or specification without notice. w w w . t a d h s a t e e . u 4 m o c -1- Rev. 0.6 (Sep. 1998) www.DataSheet4U.com KM416S1020C Revision History Revision 0.6 (September 10, 1998) CMOS SDRAM Removed KM416S1020C-H/L product (-H: 100MHz @ CL=2, -L: 100MHz @ CL3 ) Changed the clock cycle time of KM416S1020C-8 @ CL2 from 12ns to 10ns, accordingly, the AC and DC parameters of KM416S1020C-8 @ CL2 are changed in AC/DC CHARACTERISTICS. For this part, the VDD condition of AC Operating Test is 3.135V ~ 3.6V Changed ICC1 of KM416S1020C-7 @ CL2 from 115mA to 120mA in DC CHARACTERISTICS. Changed ICC1 of KM416S1020C-10 @ CL3 from 80mA to 85mA in DC CHARACTERISTICS. Changed tRDL of KM416S1020C-10 @ CL3 from 2CLK to 1CLK in OPERATING AC PARAMETER. Removed CL2 from KM416S1020C-6 Revision 0.5 (July 13, 1998) - Prelimianry Added -6(166MHz) binning product. For this part, the VDD condition of AC Operating Test is 3.135V ~ 3.6V. Changed the clock cycle time of KM416S1020C-7 @ CL2 from 12ns to 8.7ns, accordingly, the AC and DC parameters of KM416S1020C-7 @ CL2 are changed in AC/DC CHARACTERISTICS. For this part, the VDD condition of AC Operating Test is 3.135V ~ 3.6V. Changed ICC1 of KM416S1020C-7 @ CL3 from 95mA to 105mA in DC CHARACTERISTICS. Changed DC/AC Test Output Load of KM416S1020C-7/6...