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GM71VS16403CL Dataheets PDF



Part Number GM71VS16403CL
Manufacturers Hynix Semiconductor
Logo Hynix Semiconductor
Description (GM71VS16403CL / GM71V16403C) 4M x 16-Bit CMOS DRAM
Datasheet GM71VS16403CL DatasheetGM71VS16403CL Datasheet (PDF)

GM71V16403C GM71VS16403CL 4,194,304 WORDS x 4 BIT CMOS DYNAMIC RAM Description The GM71V(S)16403C/CL is the new generation dynamic RAM organized 4,194,304 words x 4 bit. GM71V(S)16403C/CL has realized higher density, higher performance and various functions by utilizing advanced CMOS process technology. The GM71V(S)16403C/CL offers Extended Data Out (EDO) Page Mode as a high speed access mode. Multiplexed address inputs permit the GM71V(S)16403C/CL to be packaged in a standard 300 mil 24(26) p.

  GM71VS16403CL   GM71VS16403CL


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GM71V16403C GM71VS16403CL 4,194,304 WORDS x 4 BIT CMOS DYNAMIC RAM Description The GM71V(S)16403C/CL is the new generation dynamic RAM organized 4,194,304 words x 4 bit. GM71V(S)16403C/CL has realized higher density, higher performance and various functions by utilizing advanced CMOS process technology. The GM71V(S)16403C/CL offers Extended Data Out (EDO) Page Mode as a high speed access mode. Multiplexed address inputs permit the GM71V(S)16403C/CL to be packaged in a standard 300 mil 24(26) pin SOJ, and a standard 300 mil 24(26) pin plastic TSOP II. The package size provides high system bit densities and is compatible with widely available automated testing and insertion equipment. System oriented features include single power supply 3.3V +/- 0.3V tolerance, direct interfacing capability with high performance logic families such as Schottky TTL. Features * 4,194,304 Words x 4 Bit Organization * Extended Data Out Mode Capability * Single Power Supply (3.3V +/- 0.3V) * Fast Access Time & Cycle Time (Unit: ns) tRAC tCAC GM71V(S)16403C/CL-5 GM71V(S)16403C/CL-6 GM71V(S)16403C/CL-7 50 60 70 13 15 18 tRC 84 104 124 tHPC 20 25 30 * Low Power Active : 324/288/252mW (MAX) Standby : 7.2mW (CMOS level : MAX) : 0.36mW (L-version : MAX) * RAS Only Refresh, CAS before RAS Refresh, Hidden Refresh Capability * All inputs and outputs TTL Compatible * 4096 Refresh Cycles/64ms * 4096 Refresh Cycles/128ms (L-version) * Self Refresh Operation (L-version) * Battery Backup Operation (L-version) * Test Function : 16bit parallel test mode Pin Configuration VCC I/O1 I/O2 WE RAS A11 A10 A0 A1 A2 A3 1 2 3 4 5 6 26 25 24 23 22 21 VSS I/O4 I/O3 CAS OE A9 A8 A7 A6 A5 A4 VSS VCC I/O1 I/O2 WE RAS A11 A10 A0 A1 A2 A3 1 2 3 4 5 6 26 25 24 23 22 21 VSS I/O4 I/O3 CAS OE A9 A8 A7 A6 A5 A4 VSS 8 9 10 11 12 19 18 8 9 10 11 12 19 18 17 16 15 14 w w w .d h s a t a Rev0.1/Apr’01 ee . u t4 VCC 13 m o c 17 16 15 14 VCC 13 (Top View) www.DataSheet4U.com 24(26) SOJ 24(26) TSOP II GM71V16403C GM71VS16403CL Pin Description Pin A0-A11 A0-A11 I/O1-I/O4 RAS CAS Function Address Inputs Refresh Address Inputs Data Input/Data Output Row Address Strobe Column Address Strobe Pin WE OE VCC VSS NC Function Read/Write Enable Output Enable Power (+3.3V) Ground No Connection Ordering Information Type No. GM71V(S)16403CJ/CLJ-5 GM71V(S)16403CJ/CLJ-6 GM71V(S)16403CJ/CLJ-7 GM71V(S)16403CT/CLT-5 GM71V(S)16403CT/CLT-6 GM71V(S)16403CT/CLT-7 Access Time 50ns 60ns 70ns 50ns 60ns 70ns Package 300 Mil 24(26) Pin Plastic SOJ 300 Mil 24(26) Pin Plastic TSOP II Absolute Maximum Ratings Symbol TA TSTG VIN/OUT VCC IOUT PD Parameter Ambient Temperature under Bias Storage Temperature Voltage on any Pin Relative to VSS Supply Voltage Relative to VSS Short Circuit Output Current Power Dissipation Rating 0 ~ 70 -55 ~ 125 -0.5 ~ Vcc+0.5 (<=4.6V(MAX)) -0.5 ~ 4.6 50 1.0 Unit C C V V mA W Recommended DC Operating Conditions (TA = 0 ~ 70C) Symbol VCC VIH VIL Parameter Supply Voltage Input High Voltage Input Low Voltage Min 3.0 2.0 -0.3 Typ 3.3 - Max 3.6 VCC + 0.3 0.8 Unit V V V Note: All voltage referred to Vss. Rev0.1/Apr’01 GM71V16403C GM71VS16403CL DC Electrical Characteristics (VCC = 3.3V+/-0.3V, VSS = 0V, TA = 0 ~ 70C) Symbol VOH VOL ICC1 Parameter Output Level Output "H" Level Voltage (IOUT = -2mA) Output Level Output "L" Level Voltage (IOUT = 2mA) Operating Current Average Power Supply Operating Current (RAS, CAS Cycling : tRC = tRC min) Standby Current (TTL) Power Supply Standby Current (RAS, CAS = VIH, DOUT = High-Z) RAS Only Refresh Current Average Power Supply Current RAS Only Refresh Mode (tRC = tRC min) EDO Page Mode Current Average Power Supply Current EDO Page Mode (tHPC = tHPC min) Standby Current (CMOS) Power Supply Standby Current (RAS, CAS >= VCC - 0.2V, DOUT = High-Z) CAS-before-RAS Refresh Current (tRC = tRC min) 50ns 60ns 70ns 50ns 60ns 70ns 50ns 60ns 70ns 50ns 60ns 70ns Min 2.4 0 - Max VCC 0.4 90 80 70 2 90 80 70 80 70 65 1 100 90 80 70 300 5 Unit V V Note mA 1, 2 ICC2 mA ICC3 mA 2 ICC4 mA 1, 3 ICC5 mA uA 5 ICC6 mA ICC7 Battery Backup Operating Current(Standby with CBR Refresh) (CBR refresh, tRC = 31.3us, tRAS <= 0.3us, DOUT = High-Z, CMOS interface) Standby Current RAS = VIH CAS = VIL DOUT = Enable Self-Refresh Mode Current (RAS, CAS<=0.2V, DOUT=High-Z, CMOS interface) Input Leakage Current Any Input (0V<=VIN<= 4.6V) Output Leakage Current (DOUT is Disabled, 0V<=VOUT<= 4.6V) - uA mA 4,5 ICC8 1 ICC9 IL(I) IL(O) -10 -10 200 10 10 uA uA uA 5 Note: 1. ICC depends on output load condition when the device is selected. ICC(max) is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. 4. CAS = L (<=0.2) while RAS = L (<=0.2). 5. L-version. Rev0.1/Apr’01 GM71V16403C GM71VS16403CL Capacitance (VCC = 3.3V +/- 0.3V, TA = 25C) Symbol CI1 CI2 CI/O Parameter Input Capacitance (Address) Input Capacitance.


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