DatasheetsPDF.com

CY7C374I

Cypress Semiconductor

128-Macrocell Flash CPLD

74i CY7C374i UltraLogic™ 128-Macrocell Flash CPLD Features • • • • 128 macrocells in eight logic blocks 64 I/O pins 5 ...


Cypress Semiconductor

CY7C374I

File Download Download CY7C374I Datasheet


Description
74i CY7C374i UltraLogic™ 128-Macrocell Flash CPLD Features 128 macrocells in eight logic blocks 64 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogrammable™ (ISR™) Flash technology — JTAG interface Bus Hold capabilities on all I/Os and dedicated inputs No hidden delays High speed — fMAX = 125 MHz — tPD = 10 ns — tS = 5.5 ns — tCO = 6.5 ns Fully PCI compliant 3.3V or 5.0V I/O operation Available in 84-pin PLCC, 84-pin CLCC, and 100-pin TQFP packages Pin compatible with the CY7C373i Functional Description The CY7C374i is an In-System Reprogrammable Complex Programmable Logic Device (CPLD) and is part of the FLASH370i™ family of high-density, high-speed CPLDs. Like all members of the FLASH370i family, the CY7C374i is designed to bring the ease of use as well as PCI Local Bus Specification support and high performance of the 22V10 to high-density CPLDs. Like all of the UltraLogic™ FLASH370i devices, the CY7C374i is electrically erasable and In-System Reprogrammable (ISR), which simplifies both design and manufacturing flows, thereby reducing costs. The Cypress ISR function is implemented through a JTAG serial interface. Data is shifted in and out through the SDI and SDO pin. The ISR interface is enabled using the programming voltage pin (ISREN). Additionally, because of the superior routability of the FLASH370i devices, ISR often allows users to change existing logic designs while simultaneously fixing pinout assignments. The 128 macroc...




Similar Datasheet


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)