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CY7C374 Dataheets PDF



Part Number CY7C374
Manufacturers Cypress Semiconductor
Logo Cypress Semiconductor
Description 128-Macrocell Flash CPLD
Datasheet CY7C374 DatasheetCY7C374 Datasheet (PDF)

For new designs see CY7C374i CY7C374 UltraLogic™ 128-Macrocell Flash CPLD Features • • • • • • 128 macrocells in eight logic blocks 64 I/O pins 6 dedicated inputs including 4 clock pins Bus Hold capabilities on all I/Os and dedicated inputs No hidden delays High speed — fMAX = 100 MHz — tPD = 12 ns — tS = 6 ns — tCO = 7 ns • Electrically Alterable Flash technology • Available in 84-pin PLCC, 84-pin CLCC, 100-pin TQFP, and 84-pin PGA packages • Pin compatible with the CY7C373 Functional Descri.

  CY7C374   CY7C374



Document
For new designs see CY7C374i CY7C374 UltraLogic™ 128-Macrocell Flash CPLD Features • • • • • • 128 macrocells in eight logic blocks 64 I/O pins 6 dedicated inputs including 4 clock pins Bus Hold capabilities on all I/Os and dedicated inputs No hidden delays High speed — fMAX = 100 MHz — tPD = 12 ns — tS = 6 ns — tCO = 7 ns • Electrically Alterable Flash technology • Available in 84-pin PLCC, 84-pin CLCC, 100-pin TQFP, and 84-pin PGA packages • Pin compatible with the CY7C373 Functional Description The CY7C374 is a Flash erasable Complex Programmable Logic Device (CPLD) and is part of the FLASH370 family of high-density, high-speed CPLDs. Like all members of the FLASH370 family, the CY7C374 is designed to bring the ease of use and high performance of the 22V10 to high-density CPLDs. The 128 macrocells in the CY7C374 are divided between eight logic blocks. Each logic block includes 16 macrocells, a 72 x 86 product term array, and an intelligent product term allocator. The logic blocks in the FLASH370 architecture are connected with an extremely fast and predictable routing resource—the Programmable Interconnect Matrix (PIM). The PIM brings flexibility, routability, speed, and a uniform delay to the interconnect. The CY7C374 is a register intensive 128-Macrocell CPLD. Every two macrocells in the device feature an associated I/O pin, resulting in 64 I/O pins on the CY7C374. In addition, there are two dedicated inputs and four input/clock pins. Logic Block Diagram CLOCK INPUTS INPUTS 2 INPUT MACROCELLS 4 8 I/Os I/O0−I/O7 LOGIC BLOCK 36 16 36 16 36 16 36 16 PIM 4 INPUT/CLOCK MACROCELLS 4 36 16 36 16 36 16 36 16 LOGIC BLOCK 8 I/Os I/O56−I/O63 A 8 I/Os LOGIC BLOCK H LOGIC BLOCK 8 I/Os I/O8−I/O15 B 8 I/Os LOGIC BLOCK G LOGIC BLOCK 8 I/Os I/O48−I/O55 I/O16−I/O23 C 8 I/Os LOGIC BLOCK F LOGIC BLOCK 8 I/Os I/O40−I/O47 I/O24−I/O31 D E 32 I/O32−I/O39 7C374–1 Selection Guide Maximum Propagation Delay tPD (ns) Minimum Set-Up, tS (ns) Maximum Clock to Output, tCO (ncs) Maximum Supply Current, ICC (mA) w w w Cypress Semiconductor Corporation Document #: 38-03021 Rev. ** .d at h s a ee t4 c . u om 32 7C374-100 12 6 7 Commercial Military/Industrial 300 7C374-83 15 8 8 300 370 7C374-66 20 10 10 300 370 7C374L-66 20 10 10 150 • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised April 1998 www.DataSheet4U.com CY7C374 Pin Configurations PGA Bottom View L I/O63 I/O62 I/O61 I/O60 I/O59 I/O58 I/O57 I/O56 GND I/O7 I/O6 I/O5 I/O4 I/O3 GND VCC I/O2 I/O1 I/O0 VCC I/O23 I/O25 I/O26 I/O28 I/O31 I/O33 VCC I/O34 I/O36 I/O37 I/O39 PLCC/CLCC Top View I5 K I/O21 GND I/O24 I/O27 I/O30 I2 I/O32 I/O35 I/O38 GND I/O41 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 CLK0/I 0 VCC GND CLK1/I 1 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 GND 74 12 73 13 72 14 71 15 70 16 69 17 68 18 67 19 66 20 65 21 64 22 63 23 62 24 61 25 60 26 59 27 58 28 57 29 56 30 55 .


ADP3418 CY7C374 CY7C374I


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