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ICS950908 Dataheets PDF



Part Number ICS950908
Manufacturers Integrated Circuit Systems
Logo Integrated Circuit Systems
Description Programmable Timing Control Hub
Datasheet ICS950908 DatasheetICS950908 Datasheet (PDF)

Integrated Circuit Systems, Inc. ICS950908 Preliminary Product Preview Programmable Timing Control Hub™ for P4™ Recommended Application: Features/Benefits: VIA Pro266/PN266/CLE266/CM400 chipset for PIII/Tualatin/C3 • Programmable output frequency. Processor • Programmable output divider ratios. • Programmable output rise/fall time. Output Features: • Programmable output skew. • 1 - Pair of differential CPU clocks @ 3.3V (CK408)/ • Programmable spread percentage for EMI control. • 1 - Pair of d.

  ICS950908   ICS950908


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Integrated Circuit Systems, Inc. ICS950908 Preliminary Product Preview Programmable Timing Control Hub™ for P4™ Recommended Application: Features/Benefits: VIA Pro266/PN266/CLE266/CM400 chipset for PIII/Tualatin/C3 • Programmable output frequency. Processor • Programmable output divider ratios. • Programmable output rise/fall time. Output Features: • Programmable output skew. • 1 - Pair of differential CPU clocks @ 3.3V (CK408)/ • Programmable spread percentage for EMI control. • 1 - Pair of differential open drain CPU clocks (K7) • Watchdog timer technology to reset system • 2 - Push pull CPUT_CS clocks @ 2.5V if system malfunctions. • 3 - AGP @ 3.3V • Programmable watch dog safe frequency. • 7 - PCI @ 3.3V • Support I2C Index read/write and block read/write • 1 - 48MHz @ 3.3V fixed operations. • 1 - 24_48MHz @ 3.3V • Uses external 14.318MHz crystal. • 2 - REF @ 3.3V, 14.318MHz Key Specifications: • CPU_CS - CPUT/C: <±250ps • CPU_CS - AGP: <±250ps • CPU - DDR/SD: <±250ps • PCI - PCI: <500ps Frequency Table FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPUCLK MHz 160.00 164.00 166.60 170.00 175.00 180.00 185.00 190.00 66.80 100.90 133.60 200.40 66.60 100.00 200.00 133.30 AGP MHz 80.00 82.00 66.60 68.00 70.00 72.00 74.00 76.00 66.80 67.27 66.80 66.80 66.60 66.60 66.60 66.60 PCICLK MHz 40.00 41.00 33.30 34.00 35.00 36.00 37.00 38.00 33.40 33.63 33.40 33.40 32.30 33.30 33.30 33.30 Pin Configuration *FS0/REF0 1 GND 2 X1 3 X2 4 VDDAGP 5 *MODE/AGPCLK0 6 *SEL_408/K7/AGPCLK1 7 *(PCI_STOP#)AGPCLK2 8 GNDAGP 9 **FS1/PCICLK_F 10 **SEL_SDR/DDR#/PCICLK1 11 GNDPCI 13 PCICLK3 14 PCICLK4 15 VDDPCI 16 PCICLK5 17 *(CLK_STOP#)/PCICLK6 18 GND48 19 *FS3/48MHz 20 *FS2/24_48MHz 21 AVDD48 22 VDD 23 *MULTSEL/PCICLK2 12 56 Vtt_PWRGD#**/REF1 55 VDDREF 54 GND 53 CPUCLKT/CPUCLKODT 52 CPUCLKC/CPUCLKODC 51 VDDCPU3.3 50 VDDCPU2.5 49 CPUT0_CS 48 CPUT1_CS 47 GND 46 FBOUT 45 BUF_IN 44 DDRT0/SDRAM0 43 DDRC0/SDRAM1 42 DDRT1/SDRAM2 41 DDRC1/SDRAM3 40 VDD3.3_2.5 39 GND 38 DDRT2/SDRAM4 37 DDRC2/SDRAM5 36 DDRT3/SDRAM6 35 DDRC3/SDRAM7 34 VDD3.3_2.5 33 GND 32 DDRT4/SDRAM8 31 DDRC4/SDRAM9 30 DDRT5/SDRAM10 29 DDRC5/SDRAM11 MULTISEL0 Board Target Trace/Term Z 50 ohms 50 ohms Reference R, Iref = VDD/(3*Rr) Rr = 221 1%, Iref = 5.00mA Rr = 475 1%, Iref = 2.32mA Output Current Ioh = 4* I REF Ioh = 6* I REF Voh @ Z GND 24 IREF 25 *(PD#)RESET# 26 SCLK 27 SDATA 28 0 1 1.0V @ 50 0.7V @ 50 * Internal 120K pull-up resistor to VDD. ** Internal 120K pull-down resistor to GND. 56-Pin 300-mil SSOP 0653A—07/26/04 PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. ICS950908 Integrated Circuit Systems, Inc. ICS950908 Preliminary Product Preview General Description The ICS950908 is a single chip clock solution for desktop designs using the VIA Pro266/PN266/CLE266/CM400 chipset with PC133 or DDR memory. The ICS950908 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). This part incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment. Block Diagram (1:0) FBOUT Mode SEL_SDR/DDR# BUF_IN SEL_408/K7# Power Groups Pin Number VDD 55 5 16 22 23 34, 40 50 51 0653A—07/26/04 GND 2 9 13 19 24 33, 39 47 54 Description Xtal, Ref AGP [0:2], CPU digital, CPU PLL PCI [0:5], PCI_F outputs 48MHz, Fix Digital, Fix Analog Master clock, CPU Analog DDR/SDR outputs 2.5V CPUT_CS output 3.3V CPUT/C & CPUOD_T/C 2 Integrated Circuit Systems, Inc. ICS950908 Preliminary Product Preview Pin Description PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PIN NAME *FS0/REF0 GND X1 X2 VDDAGP *MODE/AGPCLK0 *SEL_408/K7/AGPCLK1 *(PCI_STOP#)AGPCLK2 GNDAGP **FS1/PCICLK_F **SEL_SDR/DDR#/PCICLK1 *MULTSEL/PCICLK2 GNDPCI PCICLK3 PCICLK4 VDDPCI PCICLK5 *(CLK_STOP#)/PCICLK6 GND48 *FS3/48MHz *FS2/24_48MHz AVDD48 VDD GND IREF PIN TYPE I/O PWR IN OUT PWR I/O I/O I/O PWR I/O I/O I/O PWR OUT OUT PWR OUT I/O PWR I/O I/O PWR PWR PWR OUT DESCRIPTION Frequency select latch input pin / 14.318 MHz reference clock. Ground pin. Crystal input, Nominally 14.318MHz. Crystal output, Nominally 14.318MHz Power supply for AGP clocks, nominal 3.3V Function select latch input pin, 1=Desktop Mode, 0=Mobile Mode / AGP clock output. CPU output type select latch input pin 0= K7, 1= CK408 / AGP clock output. Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low. This input.


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