Document
SEMICONDUCTOR
SYNERGY
6-BIT 2:1 MUX-REGISTER
SY10E167 SY100E167
SY10E167 SY100E167
FEATURES
s s s s s s s s s s s 1000MHz min. operating frequency Extended 100E VEE range of –4.2V to –5.5V 800ps max. clock to output Single-ended outputs Asynchronous Master Reset Dual clocks Fully compatible with industry standard 10KH, 100K ECL levels Internal 75KΩ input pulldown resistors ESD protection of 2000V Fully compatible with Motorola MC10E/100E167 Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E167 offer six 2:1 multiplexers followed by D flip-flops with single-ended outputs, designed for use in new, high-performance ECL systems. The Select (SEL) control allows one of the two data inputs to the multiplexer to pass through. The two external clock signals (CLK1, CLK2) are gated through a logical OR operation before use as control for the six flip-flops. The selected data are transferred to the flip-flops on the rising edge of CLK1 or CLK2 (or both). The multiplexer operation is controlled by the Select (SEL) signal which selects one of the two bits of input data at each mux to be passed through. When a logic HIGH is applied to the Master Reset (MR) signal, it operates asychronously to take all outputs Q to a logic LOW.
BLOCK DIAGRAM
D0a MUX D0b D1a MUX D1b D2a MUX D2b D3a MUX D3b D4a MUX D4b D5a MUX D5b SEL CLK1 CLK2 MR SEL SEL D R SEL D R Q Q5 SEL D R Q Q4 SEL D R Q Q3 SEL D R Q Q2 D R Q Q0
PIN CONFIGURATION
D3b D3a NC VCCO
D5a D5b CLK1 CLK2 VEE MR SEL D0a
25 24 23 22 21 20 19
D4b D4a
Q
Q1
26 27 28 1 2 3 4 5 6 7 8 9 10 11
18 17
Q5 Q4 VCC Q3 Q2 VCCO Q1
TOP VIEW PLCC J28-1
16 15 14 13 12
D0b
D1a D1b
PIN NAMES
Pin D0a–D5a D0b–D5b SEL CLK1, CLK2 MR Q0–Q5 VCCO Function Input Data a Input Data b Select Input Clock Inputs Master Reset Data Outputs VCC to Output
Rev.: C Amendment: /1
© 1999 Micrel-Synergy
5-127
VCCO Q0
Issue Date: February, 1998
D2a D2b
SEMICONDUCTOR
SYNERGY
SY10E167 SY100E167
TRUTH TABLE
SEL H L Data a b
DC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = 0°C Symbol IIH IEE Parameter Input HIGH Current Power Supply Current 10E 100E — — 94 94 113 113 — — 94 94 113 113 — — 94 108 113 130 — — 150 TA = +25°C — — 150 TA = +85°C Max. 150 Unit µA mA Condition — — — — Min. Typ. Max. Min. Typ. Max. Min. Typ.
AC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = 0°C Symbol fMAX tPLH tPHL tS Parameter Max. Toggle Frequency Propagation Delay to Output CLK MR Set-up Time D SEL Hold Time D SEL Reset Recovery Time Minimum Pulse Width CLK, MR Within-Device Skew Rise/Fall Time 20% to 80% 1000 1400 450 450 100 275 300 75 750 400 — 300 650 650 –50 125 50 –125 550 — 75 450 — 800 850 — — — — — — — 800 TA = +25°C 1000 1400 450 450 100 275 300 75 750 400 — 300 650 650 –50 125 50 –125 550 — 75 450 — 800 850 — — — — — — — 800 TA = +85°C Max. — 800 850 ps 100 275 300 75 750 400 — 300 –50 125 50 –125 550 — 75 450 — — ps — — — — — 800 ps ps ps ps — — 1 — — — Unit MHz ps 450 450 650 650 Condition — — 1000 1400
Min. Typ. Max. Min. Typ.
Max. Min. Typ.
tH
tRR tPW tskew tr tf
NOTE: 1. Within-device skew is defined as identical transitions on similar paths through a device.
PRODUCT ORDERING CODE
Ordering Code SY10E167JC SY10E167JCTR SY100E167JC SY100E167JCTR Package Type J28-1 J28-1 J28-1 J28-1 Operating Range Commercial Commercial Commercial Commercial
5-128
SEMICONDUCTOR
SYNERGY
SY10E167 SY100E167
28 LEAD PLASTIC LEADED CHIP CARRIER (J28-1)
5-129
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