Micrel, Inc.
2.5V/3.3V/5V 1:5 LVPECL/PECL/ ECL/HSTL 2GHz CLOCK DRIVER WITH 2:1 DIFFERENTIAL INPUT MUX
Precision Edge®
PrecisioSnYE10d0gEeP1®4U SY100EP14U
FEATURES
• Guaranteed AC parameters over temp/voltage:
• > 2GHz fMAX • < 25ps within-device skew • < 275ps tr/tf time • < 525ps prop delay
• 2:1 Differential MUX input • Flexible supply voltage: 2.5V/3.3V/5V • Wide operating temperature range: –40°C to +85°C • VBB reference for single-ended or AC-coupled
PECL inputs
• 100K ECL compatible outputs • Inputs accept PECL/LVPECL/ECL/HSTL logic • 75kΩ internal input pull-down resistors • Available in a 20-Pin TSSOP package
ECL Pro™
DESCRIPTION
The SY100EP14U is a high-speed, 2GHz differential
PECL/ECL 1:5 fanout buffer optimized for ultra-low skew
applications. Within device skew is guaranteed to be less
than 25ps over temperature and supply voltage. The wide
supply voltage operation allows this fanout buffer to operate
in 2.5V, 3.3V, and 5V systems. A VBB reference is included for single-supply or AC-coupled PECL/ECL input
applications, thus eliminating resistor networks. When
interfacing to a single-ended or AC-coupled PECL/ECL input
signal, bypass
connect the VBB pin to the pin to VCC through a
the unused /CLK 0.01µF capacitor.
pin,
and
The SY100EP14U features a 2:1 input MUX, making it
an ideal solution for redundant clock switchover applications.
If only one input pair is used, the other pair may be left
floating. In addition, this device includes a synchronous
enable pin that forces the outputs into a fixed logic state.
Enable or disable state is initiated only after the outputs are
in a LOW state, thus eliminating the possibility of a “runt”
clock pulse.
The SY100EP14U I/O are fully differential and 100K ECL
compatible. Differential 10K ECL logic can interface directly
into the SY100EP14U inputs.
The SY100EP14U is part of Micrel’s high-speed clock
synchronization family. For applications that require a
different I/O combination, consult the Micrel website at
www.micrel.com, and choose from a comprehensive product
line of high-speed, low-skew fanout buffers, translators, and
clock generators.
ECL Pro is a trademarks of Micrel, Inc. Precision Edge is a registered trademarks of Micrel, Inc.
M9999-060910
[email protected] or (408) 955-1690
1
Rev.: G
Amendment: /0
Issue Date: May 2010
Micrel, Inc.
Precision Edge® SY100EP14U
PACKAGE/ORDERING INFORMATION
VCC /EN VCC /CLK1CLK1 VBB /CLK0CLK0 SEL VEE 20 19 18 17 16 15 14 13 12 11 D 10 Q
1 2 3 4 5 6 7 8 9 10 Q0 /Q0 Q1 /Q1 Q2 /Q2 Q3 /Q3 Q4 /Q4
20-Pin TSSOP
Ordering Information(1)
Part Number
Package Type
Operating Range
Package Marking
SY100EP14UK4C SY100EP14UK4CTR(2)
K4-20-1 K4-20-1
Commercial Commercial
XEP14U XEP14U
SY100EP14UK4I
K4-20-1
Industrial
XEP14U
SY100EP14UK4ITR(2)
K4-20-1
Industrial
XEP14U
SY100EP14UK4G(3)
K4-20-1
Industrial
XEP14U with Pb-Free bar line indicator
SY100EP14UK4GTR(2, 3)
K4-20-1
Industrial
XEP14U with Pb-Free bar line indicator
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only. 2. Tape and Reel.
3. Pb-Free package is recommended for new designs.
M9999-060910
[email protected] or (408) 955-1690
2
Micrel, Inc.
Precision Edge® SY100EP14U
PIN DESCRIPTION
Pin CLK0, /CLK0 CLK1, /CLK1
Q0 to Q4 /Q0 to /Q4 /EN
SEL
VBB
VCC VEE
Function
PECL, LVPECL, ECL, LVECL, HSTL Clock or Data Inputs. Internal 75kΩ pull-down resistors on CLK0, CLK1, and internal 75kΩ pull-up and 75kΩ pull-down resistors or
/CLK0, /CLK1. For single-ended applications, connect signal into CLK0 and/or CLK1 inputs. /CLK0, /CLK1
default condition is VCC/2 when left floating. CLK0, CLK1 default condition is LOW when left floating.
LVPECL, terminate
PECL, ECL the unused
Differential output with
Outputs: Terminate 50Ω to VCC–2V
with
50Ω
to
VCC–2V.
For
single-ended
applications,
LVPECL, /QOUT will
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when left floating. The internal latch is clocked on the falling edge of the input clock (CLK0, CLK1)
LVPECL, PECL, ECL compatible 2:1 Mux input signal select: When SEL is LOW, CLK0 input pair is selected. When SEL is HIGH, CLK1 input pair is selected. Includes a 75kΩ pull-down. Default state is LOW and CLK0 is selected.
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or VCC.
For single-ended LVTTL inputs, bypass to GND. Max. sink/source current is 0.5mA.
Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitors.
Negative Power Supply: LVPECL, PECL applications, connect to GND.
TRUTH TABLE(1)
CLK0
CLK1
CLK_SEL
/EN
LX
LL
HX
LL
XL
HL
XH
HL
XX
XH
Note 1. On next negative transition .