CLOCK DRIVER QUAD D-TYPE FLIP-FLOP WITH MATCHED PROPAGATION DELAYS
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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Clock Driver Quad D-Type Flip-Flop
MC...
Description
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document from Logic Marketing
Clock Driver Quad D-Type Flip-Flop
MC74F1803
With Matched Propagation Delays
The MC74F1803 is a high–speed, low–power, quad D–type flip–flop featuring separate D–type inputs and inverting outputs with closely matched propagation delays. With a buffered clock (CP) input that is common to all flip–flops, the MC74F1803 is useful in high–frequency systems as a clock driver, providing multiple outputs that are synchronous. Because of the matched propagation delays, the duty cycles of the output waveforms in a clock driver application are symmetrical within 2.0 nanoseconds.
CLOCK DRIVER QUAD D–TYPE FLIP–FLOP WITH MATCHED PROPAGATION DELAYS
Edge–Triggered D–Type Inputs Buffered Positive Edge–Triggered Clock Matched Outputs for Synchronous Clock Driver Applications Outputs Guaranteed for Simultaneous Switching
14 1
N SUFFIX PLASTIC CASE 646–06
Pinout: 14–Lead Plastic (Top View)
VCC 14 NC 13 O3 12 D3 11 D2 10 O2 9 CP 8
14 1
D SUFFIX SOIC CASE 751A–03
LOGIC SYMBOL
1 GND 2 NC 3 O0 4 D0 5 D1 6 O1 7 GND 4 D0 8 CP O0 D2 D3 3 CP CP D Q CP D Q CP D Q CP D Q VCC = PIN 14 GND = PINS 1 AND 7 NC = PINS 2 AND 13 6 9 12 O1 O2 O3 5 D1 10 D2 11 D3
LOGIC DIAGRAM
D0 D1
O0
O1
O2
O3
VCC = Pin 14; GND = Pins 1,7; NC = Pins 2, 13 NOTE: This diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
7/95
© Motorola, Inc. 1995
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