Document
DS3251/DS3252/DS3253/DS3254 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
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GENERAL DESCRIPTION
The DS3251 (single), DS3252 (dual), DS3253 (triple), and DS3254 (quad) line interface units (LIUs) perform the functions necessary for interfacing at the physical layer to DS3, E3, or STS-1 lines. Each LIU has independent receive and transmit paths and a built-in jitter attenuator. An on-chip clock adapter generates all line-rate clocks from a single input clock. Control interface options include 8-bit parallel, SPI, and hardware mode.
FEATURES
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Pin-Compatible Family of Products Each Port Independently Configurable Receive Clock and Data Recovery for Up to 380 meters (DS3), 440 meters (E3), or 360 meters (STS-1) of 75W Coaxial Cable Standards-Compliant Transmit Waveshaping Three Control Interface Options: 8-Bit Parallel, SPI, and Hardware Mode Built-In Jitter Attenuators can be Placed in Either the Receive or Transmit Paths Jitter Attenuators Have Provisionable Buffer Depth: 16, 32, 64, or 128 Bits Built-In Clock Adapter Generates All Line-Rate Clocks from a Single Input Clock (DS3, E3, STS-1, OC-3, 19.44MHz, 38.88MHz, 77.76MHz) B3ZS/HDB3 Encoding and Decoding Minimal External Components Required Local and Remote Loopbacks Low-Power 3.3V Operation (5V Tolerant I/O) Industrial Temperature Range: -40°C to +85°C Small Package: 144-Pin, 13mm x 13mm Thermally Enhanced CSBGA Drop-In Replacement for DS3151/52/53/54 LIUs IEEE 1149.1 JTAG Support
APPLICATIONS
SONET/SDH and PDH Multiplexers Digital Cross-Connects Access Concentrators ATM and Frame Relay Equipment Routers PBXs DSLAMs CSU/DSUs
FUNCTIONAL DIAGRAM
EACH LIU LINE IN DS3, E3, OR STS-1 RXP RXN CLK DATA RECEIVE CLOCK AND DATA CONTROL STATUS TRANSMIT CLOCK AND DATA
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Features continued on page 5.
Dallas Semiconductor DS325x
ORDERING INFORMATION
PART DS3251 DS3251N DS3252 DS3252N DS3253 DS3253N DS3254 DS3254N LIU 1 1 2 2 3 3 4 4 TEMP RANGE 0°C to +70°C -40°C to +85°C 0°C to +70°C -40°C to +85°C 0°C to +70°C -40°C to +85°C 0°C to +70°C -40°C to +85°C PIN-PACKAGE 144 TE-CSBGA 144 TE-CSBGA 144 TE-CSBGA 144 TE-CSBGA 144 TE-CSBGA 144 TE-CSBGA 144 TE-CSBGA 144 TE-CSBGA
LINE OUT DS3, E3, OR STS-1
TXP TXN
CLK DATA
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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REV: 061705
DS3251/DS3252/DS3253/DS3254
TABLE OF CONTENTS
1. 2. 3. 4. 5. 6. 7. 8. STANDARDS COMPLIANCE ......................................................................................................... 6 DETAILED DESCRIPTION ............................................................................................................. 7 APPLICATION EXAMPLE ...........................................................................................................