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ICS87354I Dataheets PDF



Part Number ICS87354I
Manufacturers Integrated Circuit Systems
Logo Integrated Circuit Systems
Description CLOCK GENERATOR
Datasheet ICS87354I DatasheetICS87354I Datasheet (PDF)

PRELIMINARY Integrated Circuit Systems, Inc. ICS87354I ÷4/÷5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL CLOCK GENERATOR FEATURES • 1 differential 2.5V/3.3V LVPECL / ECL output • 1 CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum output frequency: 250MHz • Input frequency: >1GHz • Translates any single ended input signal to 3.3V LVPECL levels with resistor bias on nCLK input • Output skew: 38ps (maximum) • Part-to-part sk.

  ICS87354I   ICS87354I


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PRELIMINARY Integrated Circuit Systems, Inc. ICS87354I ÷4/÷5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL CLOCK GENERATOR FEATURES • 1 differential 2.5V/3.3V LVPECL / ECL output • 1 CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum output frequency: 250MHz • Input frequency: >1GHz • Translates any single ended input signal to 3.3V LVPECL levels with resistor bias on nCLK input • Output skew: 38ps (maximum) • Part-to-part skew: 375ps (maximum) • Propagation delay: 2.1ns (maximum) • LVPECL mode operating voltage supply range: VCC = 2.375V to 3.8V, VEE = 0V • ECL mode operating voltage supply range: VCC = 0V, VEE = -2.375V to -3.8V • -40°C to 85°C ambient operating temperature GENERAL DESCRIPTION The ICS87354I is a high performance ÷4/÷5 Differential-to-2.5V/3.3V ECL/LVPECL Clock GeneraHiPerClockS™ tor and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The CLK, nCLK pair can accept most standard differential input levels. The ICS87354I is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and part-to-part skew characteristics make the ICS87354I ideal for those clock distribution applications demanding well defined performance and repeatability. ,&6 BLOCK DIAGRAM CLK nCLK R ÷4 ÷5 0 1 Q nQ PIN ASSIGNMENT CLK nCLK MR F_SEL 1 2 3 4 8 7 6 5 Vcc Q nQ VEE MR ICS87354I 8-Lead SOIC 3.90mm x 4.90mm x 1.37mm package body M Package Top View F_SEL The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 87354AMI www.icst.com/products/hiperclocks.html 1 REV. A JUNE 27, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS87354I ÷4/÷5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL CLOCK GENERATOR Type Input Input Input Input Power Output Power Pullup Description TABLE 1. PIN DESCRIPTIONS Number 1 2 3 4 5 6, 7 8 Name CLK nCLK MR F_SEL VEE Q, nQ VCC Pulldown Non-inver ting differential clock input. Inver ting differential clock input. Master reset. When LOW, outputs are enabled. When HIGH, Pulldown divider is reset forcing Q output LOW and nQ output HIGH. LVCMOS / LVTTL interface levels. Selects divider value for Q, nQ outputs as described in table 3. Pulldown LVCMOS / LVTTL interface levels. Negative supply pin. Differential output pair. LVPECL interface levels. Positive supply pin. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF KΩ KΩ TABLE 3. FUNCTION TABLE MR 1 0 0 F_SEL X 0 1 Divide Value Reset: Q output low, nQ output high ÷4 ÷5 CLK MR Q FIGURE 1. TIMING DIAGRAM 87354AMI www.icst.com/products/hiperclocks.html 2 REV. A JUNE 27, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS87354I ÷4/÷5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL CLOCK GENERATOR 4.6V -0.5V to VCC + 0.5 V 50mA 100mA 112.7°C/W (0 lfpm) -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, θJA Storage Temperature, TSTG TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0, TA = -40°C TO 85°C Symbol VCC IEE Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 2.375 Typical 3.3 TBD Maximum 3.8 Units V mA TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0, TA = -40°C TO 85°C Symbol Parameter VIH VIL IIH IIL Input High Voltage Input Low Voltage Input High Current Input Low Current MR, F_SEL MR, F_SEL VCC = VIN = 3.8V VCC = 3.8V, VIN = 0V -5 Test Conditions Minimum 2 -0.3 Typical Maximum VCC + 0.3 0.8 150 Units V V µA µA TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0, TA = -40°C TO 85°C Symbol IIH IIL VPP Parameter Input High Current Input Low Current CLK nCLK CLK nCLK Test Conditions VCC = VIN = 3.8V VCC = VIN = 3.8V VCC = 3.8V, VIN = 0V VCC = 3.8V, VIN = 0V -5 -150 1.3 VCC - 0.85 Minimum Typical Maximum 150 5 Units µA µA µA µA V V Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VCMR VEE + 0.5 NOTE 1, 2 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VCC .


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