KM732V688L

PRELIMINARY KM732V688/L Document Title 64Kx32-Bit Synchronous Pipelined Burst SRAM, 3.3V Power Datasheets for 100QFP/TQFP 64Kx32 Synchronous SRAM Revision History Rev. No. Rev. 0.0 Rev. 1.0 Rev. 2.0 History Initial draft Final spec release Change tOE value form 6.0 to 5.0 at tCYC 13ns. Change tCD value from 8.0 to 7.0 , tOE value form 7.0 to 5.0 at tCYC 15ns. Draft Date Jan. 19.1996 May. 25. 1997 Jun. 25. 1998 Remark Preliminary Final Final The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -1- Jun. 1998 Rev 2.0 PRELIMINARY KM732V688/L FEATURES Synchronous Operation. 2 Stage Pipelined operation with 4 Burst. On-Chip Address Counter. Self-Timed Write Cycle. On-Chip Address and Control Registers. VDD=3.3V-5%/+10% Power Supply I/O Supply Voltage : 3.3V-5%/+10% 5V Tolerant Inputs except I/O Pins. Byte Writable Function. Global Write Enable Controls a full bus-width write. Power Down State via ZZ Signal. Asynchronous Output Enable Control. ADSP, ADSC, ADV Burst Control Pins. LBO Pin allows a choice of either a interleaved burst or a linear burst. Three Chip Enables for simple depth expansion with No Data Contention ...