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UPD4481181 Dataheets PDF



Part Number UPD4481181
Manufacturers NEC
Logo NEC
Description (UPD4481161/1181/1321/1361) 8M-BIT ZEROSB SRAM
Datasheet UPD4481181 DatasheetUPD4481181 Datasheet (PDF)

DATA SHEET MOS INTEGRATED CIRCUIT µPD4481161, 4481181, 4481321, 4481361 8M-BIT ZEROSBTM SRAM FLOW THROUGH OPERATION Description The µPD4481161 is a 524,288-word by 16-bit, the µPD4481181 is a 524,288-word by 18-bit, the µPD4481321 is a 262,144-word by 32-bit and the µPD4481361 is a 262,144-word by 36-bit ZEROSB static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. The µPD4481161, µPD4481181, µPD4481321 and µPD4481361 are optimized to eliminate dead cy.

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DATA SHEET MOS INTEGRATED CIRCUIT µPD4481161, 4481181, 4481321, 4481361 8M-BIT ZEROSBTM SRAM FLOW THROUGH OPERATION Description The µPD4481161 is a 524,288-word by 16-bit, the µPD4481181 is a 524,288-word by 18-bit, the µPD4481321 is a 262,144-word by 32-bit and the µPD4481361 is a 262,144-word by 36-bit ZEROSB static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. The µPD4481161, µPD4481181, µPD4481321 and µPD4481361 are optimized to eliminate dead cycles for read to write, or write to read transitions. These ZEROSB static RAMs integrate unique synchronous peripheral circuitry, 2-bit burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single clock input (CLK). The µPD4481161, µPD4481181, µPD4481321 and µPD4481361 are suitable for applications which require synchronous operation, high speed, low voltage, high density and wide bit configuration, such as buffer memory. ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”). In the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal operation. The µPD4481161, µPD4481181, µPD4481321 and µPD4481361 are packaged in 100-pin PLASTIC LQFP with a 1.4 mm package thickness for high density and low capacitive loading. Features • Low voltage core supply : VDD = 3.3 ± 0.165 V (-A65, -A75, -A85, -A65Y, -A75Y, -A85Y) VDD = 2.5 ± 0.125 V (-C75, -C85, -C75Y, -C85Y) • Synchronous operation • Operating temperature : TA = 0 to 70 °C (-A65, -A75, -A85, -C75, -C85) TA = −40 to +85 °C (-A65Y, -A75Y, -A85Y, -C75Y, -C85Y) • 100 percent bus utilization • Internally self-timed write control • Burst read / write : Interleaved burst and linear burst sequence • Fully registered inputs and outputs for flow through operation • All registers triggered off positive clock edge • 3.3V or 2.5V LVTTL Compatible : All inputs and outputs • Fast clock access time : 6.5 ns (133 MHz), 7.5 ns (117 MHz), 8.5 ns (100 MHz) • Asynchronous output enable : /G • Burst sequence selectable : MODE • Sleep mode : ZZ (ZZ = Open or Low : Normal operation) • Separate byte write enable : /BW1 to /BW4 (µPD4481321 and µPD4481361) /BW1 and /BW2 (µPD4481161 and µPD4481181) • Three chip enables for easy depth expansion • Common I/O using three state outputs The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. M15561EJ3V0DS00 (3rd edition) Date Published December 2002 NS CP(K) Printed in Japan The mark  shows major revised points. 2001 µPD4481161, 4481181, 4481321, 4481361 Ordering Information Part number Access Time ns Clock Frequency MHz 133 117 100 133 117 100 133 117 100 133 117 100 117 100 117 100 117 100 117 100 2.5 ± 0.125 2.5 V LVTTL 3.3 V LVTTL Note 3.3 V or 2.5 V LVTTL 3.3 V LVTTL Note 3.3 V or 2.5 V LVTTL 3.3 V LVTTL Note 3.3 V or 2.5 V LVTTL Core Supply Voltage V 3.3 ± 0.165 3.3 V LVTTL Note (1/2) I/O Interface Operating Temperature °C 0 to 70 100-pin PLASTIC LQFP (14 x 20) Package µPD4481161GF-A65 µPD4481161GF-A75 µPD4481161GF-A85 µPD4481181GF-A65 µPD4481181GF-A75 µPD4481181GF-A85 µPD4481321GF-A65 µPD4481321GF-A75 µPD4481321GF-A85 µPD4481361GF-A65 µPD4481361GF-A75 µPD4481361GF-A85 µPD4481161GF-C75 µPD4481161GF-C85 µPD4481181GF-C75 µPD4481181GF-C85 µPD4481321GF-C75 µPD4481321GF-C85 µPD4481361GF-C75 µPD4481361GF-C85 6.5 7.5 8.5 6.5 7.5 8.5 6.5 7.5 8.5 6.5 7.5 8.5 7.5 8.5 7.5 8.5 7.5 8.5 7.5 8.5 3.3 V or 2.5 V LVTTL Note Although 2.5V LVTTL interface can also be used, a performance becomes equivalent to -A75 (117 MHz). 2 Data Sheet M15561EJ3V0DS µPD4481161, 4481181, 4481321, 4481361 (2/2) Part number Access Time ns Clock Frequency MHz 133 117 100 133 117 100 133 117 100 133 117 100 117 100 117 100 117 100 117 100 2.5 ± 0.125 2.5 V LVTTL 3.3 V LVTTL Note 3.3 V or 2.5 V LVTTL 3.3 V LVTTL Note 3.3 V or 2.5 V LVTTL 3.3 V LVTTL Note 3.3 V or 2.5 V LVTTL Core Supply Voltage V 3.3 ± 0.165 3.3 V LVTTL Note I/O Interface Operating Temperature °C −40 to +85 Package µPD4481161GF-A65Y µPD4481161GF-A75Y µPD4481161GF-A85Y µPD4481181GF-A65Y µPD4481181GF-A75Y µPD4481181GF-A85Y µPD4481321GF-A65Y µPD4481321GF-A75Y µPD4481321GF-A85Y µPD4481361GF-A65Y µPD4481361GF-A75Y µPD4481361GF-A85Y µPD4481161GF-C75Y µPD4481161GF-C85Y µPD4481181GF-C75Y µPD4481181GF-C85Y µPD4481321GF-C75Y µPD4481321GF-C85Y µPD4481361GF-C75Y µPD4481361GF-C85Y 6.5 7.5 8.5 6.5 7.5 8.5 6.5 7.5 8.5 6.5 7.5 8.5 7.5 8.5 7.5 8.5 7.5 8.5 7.5 8.5 100-pin PLASTIC LQFP (14 x 20) 3.3 V or 2.5 V LVTTL Note Although 2.5V LVTTL interface can also be used, a performance becomes equivalent to -A75Y (117 MHz). Data Sheet M15561EJ3V0DS 3 µPD4481161, 4481181, 4481321, 4481361 Pin Conf.


UPD4481161 UPD4481181 UPD4481321


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