MT90823

MT90823 3V Large Digital Switch Data Sheet Features 2,048 × 2,048 channel non-blocking switching at 8.192 Mb/s Per-channel variable or constant throughput delay Automatic identification of ST-BUS/GCI interfaces Accept ST-BUS streams of 2.048, 4.096 or 8.192 Mb/s Automatic frame offset delay measurement Per-stream frame delay offset programming Per-channel high impedance output control Per-channel message mode Control interface compatible to Motorola nonmultiplexed CPUs Connection memory block programming 3.3V local I/O with 5V tolerant inputs and TTLcompatible outputs IEEE-1149.1 (JTAG) Test Port Ordering Information MT90823AP MT90823AL MT90823AB MT90823AG 84 Pin PLCC 100 Pin MQFP 100 Pin LQFP 120 Pin PBGA February 2003 -40 °C to +85°C Description The MT90823 Large Digital Switch has a non-blocking switch capacity of: 2,048 x 2,048 channels at a serial bit rate of 8.192 Mb/s; 1,024 x 1,024 channels at 4.096 Mb/s; and 512 x 512 channels at 2.048 Mb/s. The device has many features that are programmable on a per stream or per channel basis, including message mode, input offset delay and high impedance output control. Per stream input delay control is particularly useful for managing large multi-chip switches that transport both voice channel and concatenated data channels. In addition, the input stream can be individually calibrated for input frame offset using a dedicated pin. Applications Medium and large switching platforms CTI applicati...