ST7282

ST7282A5 - ST7282B5 ROM FROM EPROM PRELIMINARY DATASHEET s s ST72-Core Controller/Driver for max. 20 × 16, 28 × 8 or 32 × 4 LCD segments (ST7LCD4) 56 bytes LCD-RAM 864 bytes data RAM 512 bytes EEPROM (eep2a) 32Kbytes program ROM 24 digital I/O (ST7 IO3) with pull up, interrupt input, analog input, push-pull/ open drain output 36 LCD/IO combi pins (ST7 LCIO1) with pull-up, interrupt input, push-pull, open drain output, LCD output 16 bit reload timer (ST7TIM4) Watchdog Timer (ST7 WD2) 8 bit synchronous serial I/O (ST7SIO) s s s s s s s s s s s s s s Group & Block Sync Module for RDS (ST7 RDS GB) RDS filter (ST7 RDS FI) LCD Synchro IN / Out System Frequency 8.55 MHz 8 bit A/D Converter (ST7ADC2) s RDS Demodulator (ST7 RDS BD) s n n Family ST7 Issuer Ref. PG-RO Chrono 97115 7282A5B5 March 26, 1997 Previous Ref Page 1/23 Edition Target C ST7282A5 - ST7282B5 - ROM FROM EPROM 1 GENERAL DESCRIPTION Figure 1. Block Diagram S 1 6 /P D 7 S 1 5 /P D 6 S 1 4 /P D 5 S 1 3 /P D 4 S 1 2 /P D 3 S 1 1 /P D 2 S 1 0 /P D 1 S 9 /P D 0 S 8 /P F 7 S 7 /P F 6 S 6 /P F 5 S 5 /P F 4 S 4 /P F 3 S 3 /P F 2 S 2 /P F 1 S 1 /P F 0 B P 1 6 /S 0 /P G 7 B P 1 5 /S - 1/P G 6 B P 1 4 /S - 2/P G 5 B P 1 3 /S - 3/P G 4 B P 1 2 /S - 4/P G 3 B P 1 1 /S - 5/P G 2 B P 1 0 /S - 6/P G 1 B P 9 /S -7 /P G 0 Seg. Drv. PORT D ST7 LCIO VDDP VSSP VDDA VSSA PC0/AIN PC1/AIN PC2/AIN PC3/AIN PC4/AIN PC5/AIN PC6/AIN PC7/AIN PB0/AIN PB1/AIN PB2/AIN PB3/AIN PB4/AIN PB5/AIN PB6/AIN PB7/AIN PO R T C S T 7 IO 3 PO ...