Document
TH58NVG1S3AFT05
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
2GBIT (256M u 8BITS) CMOS NAND E2PROM DESCRIPTION
The TH58NVG1S3A is a single 3.3-V 2G-bit (2,214,592,512 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (2048+64) bytes x 64 pages x 2048 blocks. The device has a 2112-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 2112-byte increments. The Erase operation is implemented in a single block unit (128 Kbytes + 4Kbytes: 2112 bytes x 64 pages). The TH58NVG1S3A is a serial-type memory device which utilizes the I/O pins for both address and data input / output as well as for command inputs. The Erase and Program operations are automatically executed making the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and other systems which require high-density nonvolatile memory data storage.
FEATURES
x Organization Memory cell allay 2112 u 64K u 8 u 2 Register 2112 u 8 Page size 2112bytes Block size (128K 4K) bytes x Modes ReadResetAuto Page Program Auto Block EraseStatus Read x Mode control Serial inputoutput Command control
x Powersupply x Program/Erase Cycles x Access time Cell array to register Serial Read Cycle x Operating current Read (50 ns cycle) Program (avg.) Erase (avg.) Standby x Package TSOP I 48-P-1220-0.50 (Weight : 0.53 g typ.)
VCC 2.7 V to 3.6 V 1E5 Cycles(With ECC) 25 Psmax 50 ns min 10 mA typ. 10 mA typ. 10 mA typ. 50 PA max
PIN ASSIGNMENT (TOP VIEW)
NC NC NC NC NC GND RY/BY RE CE NC NC VCC VSS NC NC CLE ALE WE WP NC NC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 NC NC NC NC I/O8 I/O7 I/O6 I/O5 NC NC NC VCC VSS NC NC NC I/O4 I/O3 I/O2 I/O1 NC NC NC NC
PIN NAMES
I/O1 to I/O8 I/O port
CE
WE RE CLE ALE WP RY / BY GND VCC VSS
Chip enable
Write enable Read enable Command latch enable Address latch enable Write protect Ready / Busy Ground Input Power supply Ground
000707EBA1
xTOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. xThe TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk.
2003-05-19A
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TH58NVG1S3AFT05 BLOCK DIAGRAM
Status register
VCC VSS
I/O1
Address register I/O Control circuit
Column buffer Column decoder
to
I/O8
Command register
Data register Sense amp
Row address decorder
CE
Row address buffer decoder
CLE ALE WE RE WP RY / BY RY / BY HV generator Logic control Control circuit
Memory cell array
ABSOLUTE MAXIMUM RATINGS
SYMBOL VCC VIN VI/O PD TSOLDER TSTG TOPR Power Supply Voltage Input Voltage Input /Output Voltage Power Dissipation Soldering Temperature (10s) Storage Temperature Operating Temperature RATING VALUE
0.6 to 4.6 0.6 to 4.6 0.6 V to VCC 0.3 V (
UNIT V V 4.6 V) V W °C °C °C
0.3 260 -55 to 150 0 to 70
CAPACITANCE *(Ta 25°C, f 1 MHz)
SYMB0L CIN COUT Input Output PARAMETER CONDITION VIN VOUT 0V 0V MIN
MAX 20 20
UNIT pF pF
* * This parameter is periodically sampled and is not tested for every device.
xThe products described in this document are subject to the foreign exchange and foreign trade laws. xThe information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOS.