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28C64A Dataheets PDF



Part Number 28C64A
Manufacturers Turbo IC
Logo Turbo IC
Description High Speed CMOS 64K EEPROM
Datasheet 28C64A Datasheet28C64A Datasheet (PDF)

Turbo IC, Inc. 28C64A HIGH SPEED CMOS 64K ELECTRICALLY ERASABLE PROGRAMMABLE ROM 8K X 8 BIT EEPROM FEATURES: • 120 ns Access Time • Automatic Page Write Operation Internal Control Timer Internal Data and Address Latches for 64 Bytes • Fast Write Cycle Times Byte or Page Write Cycles: 10 ms Time to Rewrite Complete Memory: 1.25 sec Typical Byte Write Cycle Time: 160 µsec • Software Data Protection • Low Power Dissipation 50 mA Active Current 200 µA CMOS Standby Current • Direct Microprocessor En.

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Turbo IC, Inc. 28C64A HIGH SPEED CMOS 64K ELECTRICALLY ERASABLE PROGRAMMABLE ROM 8K X 8 BIT EEPROM FEATURES: • 120 ns Access Time • Automatic Page Write Operation Internal Control Timer Internal Data and Address Latches for 64 Bytes • Fast Write Cycle Times Byte or Page Write Cycles: 10 ms Time to Rewrite Complete Memory: 1.25 sec Typical Byte Write Cycle Time: 160 µsec • Software Data Protection • Low Power Dissipation 50 mA Active Current 200 µA CMOS Standby Current • Direct Microprocessor End of Write Detection Data Polling • High Reliability CMOS Technology with Self Redundant EEPROM Cell Endurance: 100,000 Cycles Data Retention: 10 Years • TTL and CMOS Compatible Inputs and Outputs • Single 5 V ± 10% Power Supply for Read and Programming l Operations • JEDEC Approved Byte-Write Pinout A7 NC A12 A6 A5 A4 A3 A2 A1 A0 NC I/O0 VCC NC WE A8 A9 A11 NC OE A10 CE I/O7 I/O6 NC NC A12 5 4 3 2 1 32 31 3029 6 28 7 8 9 10 11 27 26 25 24 23 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O1 GND I/O3 I/O2 NC I/O5 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE NC A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 NC A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE NC A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 DESCRIPTION: The Turbo IC 28C64A is a 8K X 8 EEPROM fabricated with Turbo’s proprietary, high reliability, high performance CMOS technology. The 64K bits of memory are organized as 8K by 8 bits. The device offers access time of 120 ns with power dissipation below 250 mW. The 28C64A has a 64-bytes page write operation enabling the entire memory to be typically written in less than 1.25 seconds. During a write cycle, the address and 1 to 64 bytes of data are internally latched, freeing the address and data bus for other microprocessor operations. The programming process is automatically controlled by the device using an internal control timer. Data polling on one or all I/O can be used to detect the end of a programming cycle. In addition, the 28C64A includes an user-optional software data write mode offering additional protection against unwanted (false) write. The device utilizes an error protected self redundant cell for extended data retention and endurance. A11 A8 WE NC A7 A5 A3 OE A9 NC VCC A12 A6 A4 2 4 6 8 10 12 14 1 3 5 7 9 11 13 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 I/O7 I/O5 I/O3 I/O2 I/O0 A1 CE I/O6 I/O4 GND I/O1 A0 A2 12 22 21 13 14 15 16 17 18 19 20 28 pins TSOP I/O4 32 pins PLCC 28 pins PDIP 28 pins SOIC (SOG) PIN DESCRIPTION ADDRESSES (A0 - A12) The Addresses are used to select an 8 bits memory location during a write or read operation. OUTPUT ENABLE (OE) The Output Enable input activates the output buffers during the read operations. CHIP ENABLES (CE) The Chip Enable input must be low to enable all read/write operation on the device. By setting CE high, the device is disabled and the power consumption is extremely low with the standby current below 200 µA. WRITE ENABLE (WE) The Write Enable input initiates the writing of data into the memory. DATA INPUT/OUTPUT (I/O0-I/O7) Data Input/Output pins are used to read data out of the memory or to write Data into the memory. Turbo IC, Inc. 28C64A DEVICE OPERATION READ: The 28C64A is accessed like a static RAM. Read operations are initiated by both CE and OE going low and terminated by either CE or OE returning high. The outputs are at the high impedance state whenever CE or OE returns high. The two line control architecture gives designers flexibility in preventing bus contention. WRITE: A write cycle is initiated when CE and WE are low and OE is high. The address is latched internally on the falling edge of CE or WE whichever occurs last. The data is latched by the rising edge of CE or WE whichever occurs first. Once a byte write cycle has been started, the internal timer automatically generates the write sequence to the completion of the write operation. PAGE WRITE OPERATION: The page write operation of 28C64A allows one to 64 bytes of data to be serially loaded into the device and then simultaneously written into memory during the internally generated write cycle. After the first byte has been loaded, successive bytes of data may be loaded until the full page of 64 bytes is loaded. Each new byte to be written must be loaded within 200 µs of the previously loaded byte. The page address defined by the addresses A6-A12 is latched by the first CE or WE falling edge which initiates a writing cycle and they will stay latched until the completion of the page write. Any changes in the page addresses during the load-write cycle will not affect the initially latched page addresses. Addresses A0 A5 are used to define which bytes will be loaded and written within the 64 bytes page. The bytes may be loaded in any order that is convenient to the user. The content of a loaded byte may be altered at any time during the loading cycle if th.


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