24C05LN

NM24C04/05 – 4K-Bit Standard 2-Wire Bus Interface Serial EEPROM NM24C04/05 – 4K-Bit Standard 2-Wire Bus Interface Serial EEPROM February 2000 General Description The NM24C04/05 devices are 4096 bits of CMOS non-volatile electrically erasable memory. These devices conform to all specifications in the Standard IIC 2-wire protocol and are designed to minimize device pin count, and simplify PC board layout requirements. The upper half (upper 2Kbit) of the memory of the NM24C05 can be write protected by connecting the WP pin to VCC. This section of memory then becomes unalterable unless WP is switched to VSS. This communications protocol uses CLOCK (SCL) and DATA I/O (SDA) lines to synchronously clock data between the master (for example a microprocessor) and the slave EEPROM device(s). The Standard IIC protocol allows for a maximum of 16K of EEPROM memory which is supported by the Fairchild family in 2K, 4K, 8K, and 16K devices, allowing the user to configure the memory as the application requires with any combination of EEPROMs. In order to implement higher EEPROM memory densities on the IIC bus, the Extended IIC protocol must be used. (Refer to the NM24C32 or NM24C65 datasheets for more information.) Fairchild EEPROMs are designed and tested for applications requiring high endurance, high reliability and low power consumption. Block Diagram VCC VSS WP SDA SCL START STOP LOGIC SLAVE ADDRESS REGISTER & COMPARATOR CONTROL LOGIC Features I Extended operating voltage 2.7V – 5...