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M470L3224FU0 Dataheets PDF



Part Number M470L3224FU0
Manufacturers Samsung semiconductor
Logo Samsung semiconductor
Description DDR SDRAM SODIMM
Datasheet M470L3224FU0 DatasheetM470L3224FU0 Datasheet (PDF)

128MB, 256MB SODIMM Pb-Free DDR SDRAM DDR SDRAM SODIMM 200pin Unbuffered SODIMM based on 256Mb F-die 64 / 72-bit (Non ECC / ECC) 66 TSOP(II) with Pb-Free (RoHS compliant) Revision 1.2 Oct. 2004 Revision 1.2 Oct. 2004 128MB, 256MB SODIMM Pb-Free Revision History Revision 1.0 (February, 2004) - First release Revision 1.1 (March, 2004) - Corrected package dimension. Revision 1.2 (Oct, 2004) - Corrected typo. DDR SDRAM Revision 1.2 Oct. 2004 128MB, 256MB SODIMM Pb-Free 200Pin Non ECC / ECC S.

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128MB, 256MB SODIMM Pb-Free DDR SDRAM DDR SDRAM SODIMM 200pin Unbuffered SODIMM based on 256Mb F-die 64 / 72-bit (Non ECC / ECC) 66 TSOP(II) with Pb-Free (RoHS compliant) Revision 1.2 Oct. 2004 Revision 1.2 Oct. 2004 128MB, 256MB SODIMM Pb-Free Revision History Revision 1.0 (February, 2004) - First release Revision 1.1 (March, 2004) - Corrected package dimension. Revision 1.2 (Oct, 2004) - Corrected typo. DDR SDRAM Revision 1.2 Oct. 2004 128MB, 256MB SODIMM Pb-Free 200Pin Non ECC / ECC SODIMM based on 256Mb F-die(x16) Ordering Information Part Number M470L1624FU0-C(L)B3/A2/B0 M470L3224FU0-C(L)B3/A2/B0 M485L1624FU0-C(L)B3/A2/B0 Density 128MB 256MB 128MB Organization 16M x 64 32M x 64 16M x 72 DDR SDRAM Component Composition 16Mx16 (K4H561638F) * 4EA 16Mx16 (K4H561638F) * 8EA 16Mx16 (K4H561638F) * 5EA Height 1,250mil 1,250mil 1,250mil Operating Frequencies B3(DDR333@CL=2.5) Speed @CL2 Speed @CL2.5 CL-tRCD-tRP 133MHz 166MHz 2.5-3-3 A2(DDR266@CL=2) 133MHz 133MHz 2-3-3 B0(DDR266@CL=2.5) 100MHz 133MHz 2.5-3-3 Feature • Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • Programmable Read latency 2, 2.5 (clock) • Programmable Burst length (2, 4, 8) • Programmable Burst type (sequential & interleave) • Edge aligned data output, center aligned data input • Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh) • Serial presence detect with EEPROM • PCB : Height 1250 (mil), single(128MB), double(256MB) sided component • SSTL_2 Interface Pb-Free • RoHS compliant SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice. Revision 1.2 Oct. 2004 128MB, 256MB SODIMM Pb-Free Pin Configurations (Front side/back side) Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 DDR SDRAM Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 Front VREF VSS DQ0 DQ1 VDD DQS0 DQ2 VSS DQ3 DQ8 VDD DQ9 DQS1 VSS DQ10 DQ11 VDD CK0 /CK0 VSS Pin 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 Front DQ27 VDD CB0 CB1 VSS DQS8 CB2 VDD CB3 DU VSS CK2 /CK2 VDD CKE1 DU A12 A9 VSS A7 A5 A3 A1 VDD A10/AP BA0 /WE /CS0 *DU(A13) VSS DQ32 DQ33 VDD DQS4 Pin 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 Front DQ34 VSS DQ35 DQ40 VDD DQ41 DQS5 VSS DQ42 DQ43 VDD VDD VSS VSS DQ48 DQ49 VDD DQS6 DQ50 VSS DQ51 DQ56 VDD DQ57 DQS7 VSS DQ58 DQ59 VDD SDA SCL VDDSPD VDDID Back VREF VSS DQ4 DQ5 VDD DM0 DQ6 VSS DQ7 DQ12 VDD DQ13 DM1 VSS DQ14 DQ15 VDD VDD VSS VSS Pin 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 Back DQ31 VDD CB4 CB5 VSS DM8 CB6 VDD CB7 *DU/(RESET) VSS VSS VDD VDD CKE0 DU(BA2) A11 A8 VSS A6 A4 A2 A0 VDD BA1 /RAS /CAS /CS1 DU VSS DQ36 DQ37 VDD DM4 Pin 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 Back DQ38 VSS DQ39 DQ44 VDD DQ45 DM5 VSS DQ46 DQ47 VDD /CK1 CK1 VSS DQ52 DQ53 VDD DM6 DQ54 VSS DQ55 DQ60 VDD DQ61 DM7 VSS DQ62 DQ63 VDD SA0 SA1 SA2 DU KEY DQ16 DQ17 VDD DQS2 DQ18 VSS DQ19 DQ24 VDD DQ25 DQS3 VSS DQ26 KEY DQ20 DQ21 VDD DM2 DQ22 VSS DQ23 DQ28 VDD DQ29 DM3 VSS DQ30 Note 1. * : These pins are not used in this module. 2. Pins 71, 72, 73, 74, 77, 78, 79, 80, 83, 84 are not used on x64 module, & used on x72 module. Pin 95,122 are NC for 1Row module (M470L1624FU0, M485L1624FU0) & used for 2Row module (M470L3224FU0). Pin Description Pin Name A0 ~ A12 BA0 ~ BA1 DQ0 ~ DQ63 DQS0 ~ DQS8 CK0,CK0 ~ CK2, CK2 CKE0~CKE1 CS0~CS1 RAS CAS WE CB0 ~ CB7 Function Address input (Multiplexed) Bank Select Address Data input/output Data Strobe input/output Clock input Clock enable input Chip select input Row address strobe Column address strobe Write enable Check bit(Data-in/data-out) Pin Name DM0 ~ DM7, DM8(for ECC) VDD VDDQ VSS VREF VDDSPD SDA SCL SA0 ~ 2 NC Function Data - in mask Power supply (2.5V) Power Supply for DQS(2.5V) Ground Power supply for reference Serial EEPROM Power Serial data I/O Serial clock Address in EEPROM No connection Revision 1.2 Oct. 2004 128MB, 256MB SODIMM Pb-Free DDR SDRAM 128MB, 16M x 64 Non ECC Module (M470L1624FU0) (Populated as 1 bank of x16 DDR SDRAM Module) FUNCTIONAL BLOCK DIAGRAM CS0 DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 CS DQS4 DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I.


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