HY57V281620ELT

128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O Document Title 4Bank x 2M x 16bits Synchronous DRAM Revision History Revision No. 1.0 1.1 First Version Release 1. Corrected PIN ASSIGNMENT A12 to NC History Draft Date Dec. 2004 Jan. 2005 Remark This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.1 / Jan. 2005 1 Synchronous DRAM Memory 128Mbit (8Mx16bit) HY57V281620E(L)T(P) Series DESCRIPTION The Hynix HY57V281620E(L)T(P) series is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth. HY57V281620E(L)T(P) series is organized as 4banks of 2,097,152 x 16. HY57V281620E(L)T(P) is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a ne...