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ICS91309 Dataheets PDF



Part Number ICS91309
Manufacturers Integrated Circuit Systems
Logo Integrated Circuit Systems
Description High performance Communication Buffer
Datasheet ICS91309 DatasheetICS91309 Datasheet (PDF)

Integrated Circuit Systems, Inc. ICS91309 High Performance Communication Buffer General Description The ICS91309 is a high performance, low skew, low jitter zero delay buffer. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in communication systems operating at speeds from 10 to 133 MHz. The ICS91309 provides synchronization between the input and output. The synchronization is.

  ICS91309   ICS91309


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Integrated Circuit Systems, Inc. ICS91309 High Performance Communication Buffer General Description The ICS91309 is a high performance, low skew, low jitter zero delay buffer. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in communication systems operating at speeds from 10 to 133 MHz. The ICS91309 provides synchronization between the input and output. The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than +/- 350 pS, the part acts as a zero delay buffer. ICS91309 has two banks of four outputs controlled by two address lines. Depending on the selected address line, bank B or both banks can be put in a tri-state mode. In this mode, the PLL is still running and only the output buffers are put in a high impedance mode. The test mode shuts off the PLL and connects the input directly to the output buffers (see table below for functionality). ICS91309 comes in a 16-pin 150 mil SOIC, SSOP or 4.40mm TSSOP package. In the absence of REF input, the device will enter a powerdown mode. In this mode, the PLL is turned off and the output buffers are pulled low. Power down mode provides the lowest power consumption for a standby condition. Features • • • • • • • • • • Zero input - output delay Frequency range 10 - 133 MHz (3.3V) 5V tolerant input REF High loop filter bandwidth ideal for Spread Spectrum applications. Less than 125 ps cycle to cycle Jitter Skew controlled outputs Available in 16 pin, 150 mil SSOP, SOIC & 4.40mm TSSOP packages Skew: Group-to-Group: <215 ps Skew within Group: <100 ps Commercial temperature range: 0°C to +70°C Pin Configuration REF CLKA1 CLKA2 VDD GND CLKB1 CLKB2 FS2 1 2 16 15 CLKOUT CLKA4 CLKA3 VDD GND CLKB4 CLKB3 FS1 4 5 6 7 8 ICS91309 3 14 13 12 11 10 9 Block Diagram 16 pin SSOP, SOIC & TSSOP Functionality FS2 FS1 CLKA(1:4) CLKB(1:4) CLKOUT 0 0 1 1 0 1 0 1 Tristate Driven PLL Bypass Mode Driven Tristate Tristate PLL Bypass Mode Driven Driven Driven PLL Bypass Mode Driven Ouput PLL Source Shutdown PLL N PLL N REF PLL Y N 0093G—02/11/04 ICS91309 Pin Descriptions PIN # PIN NAME 1 REF1 2 CLKA12 3 CLKA22 4, 13 VDD 5, 12 GND 6 CLKB12 7 CLKB22 8 FS23 9 FS13 10 CLKB32 11 CLKB42 14 CLKA32 15 CLKA42 16 CLKOUT2 Notes: 1. Weak pull-down 2. Weak pull-down on all outputs 3. Weak pull-ups on these inputs PIN TYPE IN OUT OUT PWR PWR OUT OUT IN IN OUT OUT OUT OUT OUT DESCRIPTION Input reference frequency, 5V tolerant input Buffered clock output, Bank A Buffered clock output, Bank A Power Supply Ground Buffered clock output, Bank B Buffered clock output, Bank B Function select input, bit 2 Function select input, bit 1 Buffered clock output, Bank B Buffered clock output, Bank B Buffered clock output, Bank A Buffered clock output, Bank A Buffered clock output, internal feedback 0093G—02/11/04 2 ICS91309 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs (Except REF) . . . . . . . . . . . . . . GND –0.5 V to VDD + 0.5 V Logic Input REF . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to GND + 5.5 V Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input & Supply TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-10% PARAMETER SYMBOL CONDITIONS Input High Voltage VIH Input Low Voltage VIL Input High Current IIH VIN = VDD IIL VIN = 0 V Input Low Current Output High Voltage VoH IoH = -12 mA Output Low Voltage VoL IoL = 12 mA Operating Supply IDD Outputs Unloaded; REF = 66 MHz Current Powerdown Current Input Frequency Input Capacitance 1 MIN 2 TYP MAX 0.8 100 50 0.4 0.1 19 2.4 UNITS V V uA uA V V mA uA MHz pF 30 0.3 10 45 12 133 5 IDD Fi CIN REF = 0 Mhz NOTES: 1. Guaranteed by design and characterization, not 100% tested in production. 0093G—02/11/04 3 ICS91309 Electrical Characteristics - Outputs TA = 0 - 70°C; VDD = 3.3 V +/-10%; CL = 30 pF (unless otherwise specified) PARAMETER Output High Voltage Output Low Voltage Rise Time 1 Fall Time PLL Lock Time1 Output Frequency Duty Cycle 1 1 1 Jitter, Cycle-to-cycle Jitter, Absolute1 Jitter, 1-Sigma1 1 Skew, Group-to-Group Skew, Output-to-Output1 Skew, Device-to-Device1 Delay, Input-to-Output1 SYMBOL VOH VOL tr tf TLOCK f1 f1 Dt1 Dt2 tjcyc-cyc Tjabs Tj1s Tsk Tsk Tdsk-Tdsk Dr1 CONDITIONS IOH = -12 mA IOL = 12 mA Measure between 0.8 V and 2.0 V Measure between 2.0 V and 0.8 V.


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