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CBT3125 Dataheets PDF



Part Number CBT3125
Manufacturers NXP
Logo NXP
Description Quadruple FET bus switch
Datasheet CBT3125 DatasheetCBT3125 Datasheet (PDF)

INTEGRATED CIRCUITS CBT3125 Quadruple FET bus switch Product data File under Integrated Circuits — ICL03 2001 Dec 12 Philips Semiconductors Philips Semiconductors Product data Quadruple FET bus switch CBT3125 DESCRIPTION The CBT3125 quadruple FET bus switch features independent line switches. Each switch is disabled when the associated Output Enable (OE) input is HIGH. PIN CONFIGURATION 1OE 1A 1B 1 2 3 4 5 6 7 14 VCC 13 4OE 12 4A 11 4B 10 3OE 9 8 3A 3B FEATURES • Standard ’125-type pin.

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INTEGRATED CIRCUITS CBT3125 Quadruple FET bus switch Product data File under Integrated Circuits — ICL03 2001 Dec 12 Philips Semiconductors Philips Semiconductors Product data Quadruple FET bus switch CBT3125 DESCRIPTION The CBT3125 quadruple FET bus switch features independent line switches. Each switch is disabled when the associated Output Enable (OE) input is HIGH. PIN CONFIGURATION 1OE 1A 1B 1 2 3 4 5 6 7 14 VCC 13 4OE 12 4A 11 4B 10 3OE 9 8 3A 3B FEATURES • Standard ’125-type pinout (D, DB, and PW packages) • 5 Ω switch connection between two ports • TTL-compatible input levels • Latch-up testing is done to JESDEC Standard JESD78 which exceeds 500 mA 2OE 2A 2B GND SA00562 Figure 1. SO14, SSOP14, and TSSOP14 • ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 NC 1OE 1A 1B 2OE 2A 2B GND 1 2 3 4 5 6 7 8 16 VCC 15 4OE 14 4A 13 4B 12 3OE 11 3A 10 3B 9 NC SA00563 NC = no internal connection Figure 2. SSOP(QSOP)16 ORDERING INFORMATION PACKAGES 14-Pin Plastic SO 14-Pin Plastic SSOP 16-Pin Plastic SSOP(QSOP) 14-Pin Plastic TSSOP TEMPERATURE RANGE –40 to +85 °C –40 to +85 °C –40 to +85 °C –40 to +85 °C ORDER CODE CBT3125D CBT3125DB CBT3125DS CBT3125PW DRAWING NUMBER SOT108-1 SOT337-1 SOT519-1 SOT402-1 Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging. 2001 Dec 12 2 853-2309 27452 Philips Semiconductors Product data Quadruple FET bus switch CBT3125 LOGIC DIAGRAM 1A 2 3 1B FUNCTION TABLE (each bus switch) INPUT OE L FUNCTION A=B disconnect 1OE 1 H 6 2B 2A 5 2OE 4 3A 9 8 3B 3OE 10 4A 12 11 4B 4OE 13 SA00564 Pin numbers shown are for 14-pin package-types. Figure 3. CBT3125 logic diagram (positive logic) ABSOLUTE MAXIMUM RATINGS1 Over operating free-air temperature range, unless otherwise noted. SYMBOL VCC VI IK Tstg supply voltage range input voltage range continuous channel current input clamp current storage temperature range VI/O < 0 see Note 2 PARAMETER CONDITIONS MIN. –0.5 –0.5 — — –65 MAX. 7 7 128 –50 +150 UNIT V V mA mA °C NOTES: 1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. The package thermal impedance is calculated in accordance with JESD 51-7. RECOMMENDED OPERATING CONDITIONS1 SYMBOL VCC VIH VIL Tamb supply voltage high-level control input voltage low-level control input voltage operating ambient temperature in free-air PARAMETER CONDITIONS MIN. 4.5 2 — –40 MAX. 5.5 — 0.8 +85 UNIT V V V °C NOTE: 1. All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. 2001 Dec 12 3 Philips Semiconductors Product data Quadruple FET bus switch CBT3125 DC ELECTRICAL CHARACTERISTICS Over recommended operating free-air temperature range, unless otherwise noted. SYMBOL VIK II ICC ∆ICC CI CIO(OFF) VP PARAMETER Input clamp voltage Input leakage current Quiescent supply current Additional supply current per input pin (Note 2) Input capacitance Power-off leakage current Pass gate voltage CONDITIONS VCC = 4.5 V; II = –18 mA VCC = 5.5 V; VI = 5.5 V or GND VCC = 5.5 V; IO = 0; VI = VCC or GND control inputs control inputs VCC = 5.5 V; one input at 3.4 V, other inputs at VCC or GND VI = 3 V or 0 VO = 3 V or 0; OE = VCC VCC = 5.0 V; VI = 5.0 V VCC = 4.5 V; VI = 0 V; II = 64 mA ron On-resistance (Note 3) VCC = 4.5 V; VI = 0 V; II = 30 mA VCC = 4.5 V; VI = 2.4 V; II = –15 mA MIN. — — — TYP.1 — — — MAX. –1.2 ±1 3 UNIT V µA µA mA pF pF V Ω Ω Ω — — — — — — — — 1.7 3.4 3.8 5 5 10 2.5 — — — 7 7 15 NOTES: 1. All typical values are at VCC = 5 V, unless otherwise noted. Tamb = 25 °C. 2. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. 3. Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. On-state resistance is determined by the lower of the voltages of the two (A or B) terminals. AC CHARACTERISTICS Tamb = –40 to +85 °C; CL = 50 pF, unless otherwise noted. SYMBOL tpd ten tdis PARAMETER Propagation delay1 Output enable time to High and Low level Output disable time from High and Low level FROM (INPUT) A or B OE OE TO (OUTPUT) B or A A or B A or B VCC = 5 V ± 0.5 V Min — 1.0 1 Max 0.25 5.4 4.7 ns ns ns UNIT NOTE: 1. This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical on-state resistance of the switch and a load capacitance of 50 pF, when driven by an ideal voltage source (.


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