UPA2752GR

DATA SHEET MOS FIELD EFFECT TRANSISTOR µPA2752GR SWITCHING N-CHANNEL POWER MOS FET DESCRIPTION The µPA2752GR is Dual N-Channel MOS Field Effect Transistor designed for DC/DC converters and power management applications of notebook computers. PACKAGE DRAWING (Unit: mm) 8 5 1 : Source 1 2 : Gate 1 7, 8 : Drain 1 3 : Source 2 4 : Gate 2 5, 6 : Drain 2 6.0 ±0.3 4.4 +0.10 –0.05 FEATURES Dual chip type Low on-state resistance RDS(on)1 = 23.0 mΩ MAX. (VGS = 10 V, ID = 4.0 A) RDS(on)2 = 35.0 mΩ MAX. (VGS = 4.5 V, ID = 4.0 A) RDS(on)3 = 41.0 mΩ MAX. (VGS = 4.0 V, ID = 4.0 A) Low Ciss: Ciss = 480 pF TYP. Built-in G-S protection diode Small and surface mount package (Power SOP8) 1 4 5.37 MAX. 1.44 0.8 1.8 MAX. 0.15 0.05 MIN. 0.5 ±0.2 0.10 1.27 0.78 MAX. 0.40 +0.10 –0.05 0.12 M ORDERING INFORMATION PART NUMBER PACKAGE Power SOP8 µPA2752GR ABSOLUTE MAXIMUM RATINGS (TA = 25°C, All terminals are connected.) Drain to Source Voltage (VGS = 0 V) Gate to Source Voltage (VDS = 0 V) Drain Current (DC) (TC = 25°C) Drain Current (pulse) Note1 Note2 Note2 VDSS VGSS ID(DC) ID(pulse) PT PT Tch Tstg 30 ±20 ±8.0 ±32 1.7 2.0 150 –55 to +150 8 6.4 V V A A W W °C °C A mJ Gate Protection Diode Source Gate Body Diode EQUIVALENT CIRCUIT (1/2 Circuit) Drain Total Power Dissipation (1 unit) Total Power Dissipation (2 unit) Channel Temperature Storage Temperature Single Avalanche Current Single Avalanche Energy Note3 Note3 IAS EAS Notes 1. PW ≤ 10 µs, Duty cycle ≤ 1% 2 2. TA =...