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ICX285AL Dataheets PDF



Part Number ICX285AL
Manufacturers Sony Corporation
Logo Sony Corporation
Description Progressive Scan CCD Image Sensor with Square Pixel for B/W Cameras
Datasheet ICX285AL DatasheetICX285AL Datasheet (PDF)

ICX285AL Diagonal 11 mm (Type 2/3) Progressive Scan CCD Image Sensor with Square Pixel for B/W Cameras Description The ICX285AL is a diagonal 11 mm (Type 2/3) interline CCD solid-state image sensor with a square pixel array. High sensitivity and low smear are achieved through the adoption of EXview HAD CCD technology. Progressive scan allows all pixel’s signals to be output independently within approximately 1/15 second. Also, the adoption of high frame rate readout mode supports 60 frames per s.

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ICX285AL Diagonal 11 mm (Type 2/3) Progressive Scan CCD Image Sensor with Square Pixel for B/W Cameras Description The ICX285AL is a diagonal 11 mm (Type 2/3) interline CCD solid-state image sensor with a square pixel array. High sensitivity and low smear are achieved through the adoption of EXview HAD CCD technology. Progressive scan allows all pixel’s signals to be output independently within approximately 1/15 second. Also, the adoption of high frame rate readout mode supports 60 frames per second. This chip features an electronic shutter with variable charge-storage time which makes it possible to realize full-frame still images without a mechanical shutter. This chip is suitable for image input applications such as still cameras which require high resolution, etc. 20 pin DIP (Ceramic) Features • Progressive scan allows individual readout of the image signals from all pixels. • High horizontal and vertical resolution (both approximately 1024 TV-lines) still images without a mechanical shutter • Supports high frame rate readout mode (effective 256 lines output, 60 frame/s) • Square pixel • Aspect ratio: 4:3 Pin 1 • Horizontal drive frequency: 28.64 MHz 2 • High sensitivity, low smear • Low dark current, excellent anti-blooming characteristics • Continuous variable-speed shutter V • Horizontal register: 5.0 V drive Device Structure 2 • Interline CCD image sensor 40 H Pin 11 • Image size: Diagonal 11 mm (Type 2/3) • Total number of pixels: 1434 (H) × 1050 (V) approx. 1.50M pixels Optical black position • Number of effective pixels: 1392 (H) × 1040 (V) approx. 1.45M pixels (Top View) • Number of active pixels: 1360 (H) × 1024 (V) approx. 1.40M pixels • Chip size: 10.2 mm (H) × 8.3 mm (V) • Unit cell size: 6.45 µm (H) × 6.45 µm (V) • Optical black: Horizontal (H) direction: Front 2 pixels, rear 40 pixels Vertical (V) direction: Front 8 pixels, rear 2 pixels • Number of dummy bits: Horizontal 20 Vertical 3 • Substrate material: Silicon 8 * EXview HAD CCD is a trademark of Sony Corporation. EXview HAD CCD is a CCD that drastically improves light efficiency by including near infrared light region as a basic structure of HAD (Hole-Accumulation-Diode) sensor. Sony reserves the right to change products and specifications without prior notice. This information does not convery any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E00Y42A27 ICX285AL Block Diagram and Pin Configuration (Top View) GND GND Vφ2B Vφ2A Vφ3 Vφ4 10 9 8 7 6 5 4 3 2 Vertical register Note) Horizontal register Note) : Photo sensor 11 VOUT 12 VDD 13 φRG 14 Hφ2 15 Hφ1 16 φSUB 17 CSUB 18 VL 19 Hφ1 Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 *1 Symbol Vφ1 Vφ2A NC Vφ2B NC NC Vφ4 Vφ3 GND GND Description Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Pin No. 11 12 13 14 15 16 Hφ2 Vφ1 NC NC NC 1 20 Symbol VOUT VDD φRG Hφ2 Hφ1 φSUB CSUB VL Hφ1 Hφ2 Description Signal output Supply voltage Reset gate clock Horizontal register transfer clock Horizontal register transfer clock Substrate clock Substrate bias*1 Protective transistor bias Horizontal register transfer clock Horizontal register transfer clock Vertical register transfer clock Vertical register transfer clock GND GND 17 18 19 20 DC bias is generated within the CCD, so that this pin should be grounded externally through a capacitance of 0.1µF. –2– ICX285AL Absolute Maximum Ratings Item VDD, VOUT, φRG – φSUB Vφ2A, Vφ2B – φSUB Against φSUB Vφ1, Vφ3, Vφ4, VL – φSUB Hφ1, Hφ2, GND – φSUB CSUB – φSUB VDD, VOUT, φRG, CSUB – GND Against GND Vφ1, Vφ2A, Vφ2B, Vφ3, Vφ4 – GND Hφ1, Hφ2 – GND Against VL Between input clock pins Storage temperature Performance guarantee temperature Operating temperature *1 Ratings –40 to +12 –50 to +15 –50 to +0.3 –40 to +0.3 –25 to –0.3 to +22 –10 to +18 –10 to +6.5 –0.3 to +28 –0.3 to +15 to +15 –6.5 to +6.5 –10 to +16 –30 to +80 –10 to +60 –10 to +75 Unit V V V V V V V V V V V V V °C °C °C Remarks Vφ2A, Vφ2B – VL Vφ1, Vφ3, Vφ4, Hφ1, Hφ2, GND – VL Voltage difference between vertical clock input pins Hφ1 – Hφ2 Hφ1, Hφ2 – Vφ4 *1 +24 V (Max.) when clock width < 10 µs, clock duty factor < 0.1%. +16 V (Max.) is guaranteed for power-on and power-off. Bias Conditions Item Supply voltage Protective transistor bias Substrate clock Reset gate clock DC characteristics Item Supply current *2 Symbol VDD VL φSUB φRG Min. 14.55 Typ. 15.0 *2 *3 *3 Max. 15.45 Unit V Remarks Symbol IDD Min. Typ. 9 Max. 11 Unit mA Remarks *3 VL setting is the VVL voltage of the vertical clock waveform, or the same voltage as the VL power supply for the V driver should be used. Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is genera.


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