ATC18RHA

Features Comprehensive Library of Standard Logic and I/O Cells ATC18RHA Core and I/O Cells Designed to Operate with VDD = 1.8V Sparing 0.15V as Main Target Operating Conditions IO33 Pad Libraries Provide Interfaces to 3V Environments Memory Cells Compiled to the Precise Requirements of the Design EDAC Library SEU Hardened DFF’s Cold Sparring Buffers High Speed LVDS Buffers PCI Buffers Predefined Die Sizes to Accommodate Specified Packages and ESA (European Space Agency) Multi-project Wafer Services MQFP Package Up to 352 Pins (340 Signal Pins) MCGA Packages Up to 625 Pins (581 Signal Pins) Assurance Programs Will Allow – Testing Flight Models to SCC B and QML Q & V – Monitoring Heavy Ions Latch-up Immunity and Total Dose Capability Better than 100 Krads. Rad. Hard 0.18 µm CMOS Cell-based ASIC for Space Use ATC18RHA Advance Information Description The Atmel ATC18RHA is fabricated on a proprietary 0.18 µm, up to six-layer-metal CMOS process intended for use with a supply voltage of 1.8V ± 0.15V. Table 1 shows the range for that Atmel library cells have been characterized. Table 1. Recommended Operating Conditions Symbol VDD VDD3.3 VI VO TEMP Parameter DC Supply Voltage DC Supply Voltage DC Input Voltage DC Output Voltage Operating Free Air Temperature Range Military Conditions Core and Standard I/Os 3V Interface I/Os Min 1.65 3 0 0 -55 Typ 1.8 3.3 Max 1.95 3.6 VDD VDD +125 Unit V V V V °C The Atmel cell libraries and megacell compilers have been de...