AN7187

Philips Semiconductors Clock and synchronization signals of SAA7187 and SAA7188 Application note for digital video encoder Author: Leo Warmuth 1.0 INTRODUCTION The devices of the SAA7187/88 family of video encoders can be used in a variety of applications differing regarding the signal flow of timing information. Video timing is defined by clock signals, synchronization signals and blanking signals. The video encoder ICs can generate these signals by itself (master mode), or can accept them as input (slave mode). The master/slave characteristic can be chosen independently for clock and sync-signals. This application note describes the various clock and synchronization signals, their functions, and how to select and program them. The timing relation of some of these signals is programmable. An application example shows a possible configuration. crystal oscillator, or receive the clock signals from external. In remote genlock mode, LLC and CREF can be fed from one of the Philips digital decoder (DMSD), but must then be accompanied by RTC signal (real time control information). 2.2 External Clock In the “clock slave mode” case, i.e., if clock is provided from external into LLC pin 38, a CREF-like signal can optionally be applied to pin 39, but this is not required. If the IC sees a toggling signal, i.e., edges, at pin 39, CREF will contribute to re-synchronization of the internal horizontal counter (once per line) and – by that – defines the active data phases in the 16 bit wi...