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NetMos
Technology
Features • Single 5-V Operation • Low Power • PCI compatible Dual UART • Pin-to-Pin compatible to Nm9735 • 16 byte transmit-receive FIFO (UART) • Selectable receive trigger levels • Programmable baud rate generator • Modem control signals • 5, 6, 7, 8 Bit characters selection • Even, Odd, No parity, or Force parity generations • Status report capability • Compatible with 16C550 • Multi-mode compatible controller (SPP, PS2, EPP, ECP) • Fast data rates up to 1.5 Mbytes/s (parallel port) • Fast data rates up to 1 Mbytes/s (serial ports) • On chip oscillator • Re-map function for legacy ports • 16 Byte FIFO (parallel) • Microsoft Compatible • Software programmable mode selects • 128-pin VQFP package Applications • Printer server • Portable backup units • Printer interface • Embedded applications • High speed modems • Monitoring equipment • Add on I/O cards • Serial networking
Nm9835
PCI + Dual UART and 1284 Printer Port
General Description The Nm9835 is a PCI based dual-channel high performance UART with Enhanced bi-directional parallel controller. The Nm9835 offers 16 byte transmit and receive FIFO for each UART channel and 16 byte FIFO for printer channel. The Nm9835 perform serial-to-parallel conversions on data received from a peripheral device, and parallel-to-serial conversion on data received from its CPU. In addition Nm9835 fully supports the existing Centronics printer interface as well as PS/2, EPP, and ECP modes. The Nm9835 is ideally suited for PC applications, such as high speed COM ports and parallel port. The Nm9835 is available in 128-Pin QFP package, It is fabricated in an advanced in submicron CMOS process to achieve low drain power and high speed requirements.
Ordering Information Commercial Grade Nm9835CV 128-VQFP 0° C to +70° C
Industrial Grade Nm9835EV 128-VQFP -40° C to +85° C
Rev. 1.0
Page 1-51
Nm9835
PCI + Dual UART and 1284 Printer Port
128-Pin VQFP Package
nRESET EE-CLK nDSRA nDTRA nCTSA nRTSA
NetMos
Technology
EE-DO
EE-EN
EE-CS
nINTA
nCDA
EE-DI
AD29 128 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
AD30 127
AD31 126
GND 125
GND
nRIA
GND
VCC
VCC
RXA
N.C. 124
N.C.
CLK 122
TXA
123
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
VCC AD28 AD27 AD26 AD25 AD24 GND nC/BE3 IDSEL VCC AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 VCC GND GND nC/BE2 nFRAME nIRDY nTRDY nDEVSEL nSTOP nLOCK nPERR nSERR PAR nC/BE1 GND AD15 AD14 AD13 AD12 AD11
N.C. N.C. N.C. GND PD7 PD6 PD5 PD4 GND PD3 PD2 PD1 PD0 VCC GND PE nACK nBUSY SLCT nFAULT VCC nSTROBE nAUTOFDX nINIT nSLCTIN GND TXB nDTRB nRTSB RXB nDSRB nCTSB nCDB nRIB N.C. N.C. VCC N.C.
Nm9835CV
40 AD10
41 AD9
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
VCC
AD8
nC/BE0
GND
GND
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
VCC
3XCLK
6XCLK
BCLK
12XCLK
ACLK
GND
XTAL2
XTAL1
N.C.
N.C.
Page 1-52
Rev. 1.0
NetMos
Technology
Pin Name CLK nRESET 128 122 121 Type I I Description 33 MHz PCI system clock input.
Nm9835
PCI + Dual UART and 1284 Printer Port
PCI System reset (avtice low). Resets all internal register, sequencers, and signals to a consistent state. During reset condition AD31-0, nSER are threestated. Multiplexed PCI address / data bus. A bus transaction consists of an address phase followed by one or more data phase. During the address phase AD310 contain a physical address. Write data is stable and valid when nIRDY and nTRDY are asserted (active). See AD31-29 description. See AD31-29 description. See AD31-29 description. See AD31-29 description. See AD31-29 description. Frame is driven by the current master to indicate the beginning and duration of an access. nFRAME is asserted to indicate a bus transaction is beginning. While nFRAME is active, data transfer continues. Initiator Ready. During a write, nIRDY asserted indicates that the initiator is driving valid data onto the data bus. During a read, nIRDY asserted indicates that the initiator is ready to accept data from the Nm9835. Target Ready (three-state). It is asserted when Nm9835 is ready to complete the current data phase. Nm9835 asserts nSTOP to indicate that it wishes the initiator to stop the transaction in process on the current data phase. Lock indicates an atomic operation that my require multiple transactions to complete. Initialization Device Select. It is used as a chip select during configuration read and writes transactions. Device Select (three-state). Nm9835 asserts nDEVSEL when the Nm9835 has decoded its address. Parity Error (three-state). Is used to report parity errors during all PCI trans-
AD31-29 126-128
I/O
AD28-24 AD23-16 AD15-11 AD10-8 AD7-0 nFRAME
2-6 11-18 34-38 40-42 46-53 23
I/O I/O I/O I/O I/O I
nIRDY
24
I
nTRDY nSTOP nLOCK IDSEL nDEVSE.