Document
ISO2-CMOS
MT8960/61/62/63/64/65/66/67 Integrated PCM Filter Codec
Data Sheet
Features
• • • • • • ST-BUS compatible Transmit/Receive filters & PCM Codec in one I.C Meets AT&T D3/D4 and CCITT G711 and G712 µ-Law: MT8960/62/64/67 A-Law: MT8961/63/65/67 Low power consumption: Op.: 30 mW typ. Stby.: 2.5 mW typ. Digital Coding Options: MT8964/65/66/67 CCITT Code MT8960/61/62/63 Alternative Code Digitally controlled gain adjust of both filters Analog and digital loopback Filters and codec independently user accessible for testing Powerdown mode available 2.048 MHz master clock input Up to six uncommitted control outputs ±5 V ±5% power supply
Ordering Information
MT8960/61/64/65AE MT8962/63AE MT8962/63/66/67AS MT8963ASR MT8960AE1 MT8962/63AE1 MT8962AS1 MT8963AS1 18 20 20 20 18 20 20 20 Pin Pin Pin Pin Pin Pin Pin Pin PDIP PDIP SOIC SOIC PDIP* PDIP* SOIC* SOIC*
February 2005
Tubes Tubes Tubes Tape & Reel Tubes Tubes Tubes Tubes
*Pb Free Matte Tin
-40°C to +85 °C
•
Description
Manufactured in ISO2-CMOS, these integrated filter/codecs are designed to meet the demanding performance needs of the digital telecommunications industry, e.g., PABX, Central Office, Digital telephones.
• • • • • • •
ANUL VX Transmit Filter Analog to Digital PCM Encoder Output Register DSTo
SD0 SD1 SD2 SD3 SD4 SD5 Output Register
A Register 8-Bits
CSTi CA Control Logic F1i C2i
B-Register 8-Bits
VR
Receive Filter
PCM Digital to Analog Decoder
Input Register
DSTi
VRef
GNDA
GNDD
VDD
VEE
Figure 1 - Functional Block Diagram 1
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MT8960/61/62/63/64/65/66/67
Data Sheet
MT8960/61/64/65 CSTi DSTi C2i DSTo VDD F1i CA SD3 SD2 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 18 PIN PDIP GNDD VRef GNDA VR ANUL VX VEE SD0 SD1 CSTi DSTi C2i DSTo VDD SD5 SD4 F1i CA SD3
MT8962/63/66/67 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 GNDD VRef GNDA VR ANUL VX VEE SD0 SD1 SD2
20 PIN PDIP/SOIC
Figure 2 - Pin Connections Pin Description Pin Name CSTi Description Control ST-BUS In is a TTL-compatible digital input used to control the function of the filter/codec. Three modes of operation may be effected by applying to this input a logic high (VDD), logic low (GNDD), or an 8-bit serial word, depending on the logic states of CA and F1i. Functions controlled are: powerdown, filter gain adjust, loopback, chip testing, SD outputs. Data ST-BUS In accepts the incoming 8-bit PCM word. Input is TTL-compatible. Clock Input is a TTL-compatible 2.048 MHz clock. Data ST-BUS Out is a three-state digital output driving the PCM bus with the outgoing 8-bit PCM word. Positive power Supply (+5 V). Synchronization Input is an active low digital input enabling (in conjunction with CA) the PCM input, PCM output and digital control input. It is internally sampled on every positive edge of the clock, C2i, and provid.