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MT896x Dataheets PDF



Part Number MT896x
Manufacturers Zarlink Semiconductor
Logo Zarlink Semiconductor
Description Integrated PCM Filter Codec
Datasheet MT896x DatasheetMT896x Datasheet (PDF)

ISO2-CMOS MT8960/61/62/63/64/65/66/67 Integrated PCM Filter Codec Data Sheet Features • • • • • • ST-BUS compatible Transmit/Receive filters & PCM Codec in one I.C Meets AT&T D3/D4 and CCITT G711 and G712 µ-Law: MT8960/62/64/67 A-Law: MT8961/63/65/67 Low power consumption: Op.: 30 mW typ. Stby.: 2.5 mW typ. Digital Coding Options: MT8964/65/66/67 CCITT Code MT8960/61/62/63 Alternative Code Digitally controlled gain adjust of both filters Analog and digital loopback Filters and codec independe.

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ISO2-CMOS MT8960/61/62/63/64/65/66/67 Integrated PCM Filter Codec Data Sheet Features • • • • • • ST-BUS compatible Transmit/Receive filters & PCM Codec in one I.C Meets AT&T D3/D4 and CCITT G711 and G712 µ-Law: MT8960/62/64/67 A-Law: MT8961/63/65/67 Low power consumption: Op.: 30 mW typ. Stby.: 2.5 mW typ. Digital Coding Options: MT8964/65/66/67 CCITT Code MT8960/61/62/63 Alternative Code Digitally controlled gain adjust of both filters Analog and digital loopback Filters and codec independently user accessible for testing Powerdown mode available 2.048 MHz master clock input Up to six uncommitted control outputs ±5 V ±5% power supply Ordering Information MT8960/61/64/65AE MT8962/63AE MT8962/63/66/67AS MT8963ASR MT8960AE1 MT8962/63AE1 MT8962AS1 MT8963AS1 18 20 20 20 18 20 20 20 Pin Pin Pin Pin Pin Pin Pin Pin PDIP PDIP SOIC SOIC PDIP* PDIP* SOIC* SOIC* February 2005 Tubes Tubes Tubes Tape & Reel Tubes Tubes Tubes Tubes *Pb Free Matte Tin -40°C to +85 °C • Description Manufactured in ISO2-CMOS, these integrated filter/codecs are designed to meet the demanding performance needs of the digital telecommunications industry, e.g., PABX, Central Office, Digital telephones. • • • • • • • ANUL VX Transmit Filter Analog to Digital PCM Encoder Output Register DSTo SD0 SD1 SD2 SD3 SD4 SD5 Output Register A Register 8-Bits CSTi CA Control Logic F1i C2i B-Register 8-Bits VR Receive Filter PCM Digital to Analog Decoder Input Register DSTi VRef GNDA GNDD VDD VEE Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved. MT8960/61/62/63/64/65/66/67 Data Sheet MT8960/61/64/65 CSTi DSTi C2i DSTo VDD F1i CA SD3 SD2 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 18 PIN PDIP GNDD VRef GNDA VR ANUL VX VEE SD0 SD1 CSTi DSTi C2i DSTo VDD SD5 SD4 F1i CA SD3 MT8962/63/66/67 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 GNDD VRef GNDA VR ANUL VX VEE SD0 SD1 SD2 20 PIN PDIP/SOIC Figure 2 - Pin Connections Pin Description Pin Name CSTi Description Control ST-BUS In is a TTL-compatible digital input used to control the function of the filter/codec. Three modes of operation may be effected by applying to this input a logic high (VDD), logic low (GNDD), or an 8-bit serial word, depending on the logic states of CA and F1i. Functions controlled are: powerdown, filter gain adjust, loopback, chip testing, SD outputs. Data ST-BUS In accepts the incoming 8-bit PCM word. Input is TTL-compatible. Clock Input is a TTL-compatible 2.048 MHz clock. Data ST-BUS Out is a three-state digital output driving the PCM bus with the outgoing 8-bit PCM word. Positive power Supply (+5 V). Synchronization Input is an active low digital input enabling (in conjunction with CA) the PCM input, PCM output and digital control input. It is internally sampled on every positive edge of the clock, C2i, and provides frame and channel synchronization. Control Address is a three-level digital input which enables PCM input and output and determines into which control register (A or B) the serial data, presented to CSTi, is stored. System Drive Output is an open drain output of an N-channel transistor which has its source tied to GNDA. Inactive state is open circuit. System Drive Outputs are open drain outputs of N-channel transistors which have their source tied to GNDD. Inactive state is open circuit. System Drive Outputs are “Totempole“ CMOS outputs switching between GNDD and VDD. Inactive state is logic low. Negative power supply (-5 V). Voice Transmit is the analog input to the transmit filter. Auto Null is used to integrate an internal auto-null signal. A 0.1 µF capacitor must be connected between this pin and GNDA. Voice Receive is the analog output of the receive filter. Analog ground (0 V). Voltage Reference input to D to A converter. Digital ground (0 V). DSTi C2i DSTo VDD F1i CA SD3 SD4-5 SD0-2 VEE VX ANUL VR GNDA VRef GNDD 2 Zarlink Semiconductor Inc. MT8960/61/62/63/64/65/66/67 Data Sheet MT8960/62 Digital Output 11111111 11110000 11100000 11010000 11000000 10110000 10100000 10010000 10000000 00000000 00010000 00100000 00110000 01000000 01010000 01100000 01110000 01111111 Bit 7... MSB 0 LSB -2.415V -1.207V 0V +1.207V +2.415V MT8964/66 Digital Output 10000000 10001111 10011111 10101111 10111111 11001111 11011111 11101111 11111111 01111111 01101111 01011111 01001111 00111111 00101111 00011111 00001111 00000000 Analog Input Voltage (VIN) Figure 3 - µ -Law Encoder Transfer Characteristic 3 Zarlink Semiconductor Inc. MT8960/61/62/63/64/65/66/67 Data Sheet MT8961/63 Digital Output 11111111 11110000 11100000 11010000 11000000 10110000 10100000 10010000 10000000 00000000 00010000 00100000 00110000 01000000 01010000 01100000 01110000 01111111 Bit 7... MSB 0 LSB -2.5V -1.25V 0V +1.25V +2.5V MT8965/67 Digital Output 10101010 10100101 10110101 10000101 10010101 11.


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