Document
MX29F040
4M-BIT [512KX8] CMOS EQUAL SECTOR FLASH MEMORY
FEATURES
• 524,288 x 8 only • Single power supply operation - 5.0V only operation for read, erase and program operation • Fast access time: 55/70/90/120ns • Low power consumption - 30mA maximum active current(5MHz) - 1uA typical standby current • Command register architecture - Byte Programming (7us typical) - Sector Erase 8 equal sectors of 64K-Byte each • Auto Erase (chip & sector) and Auto Program - Automatically erase any combination of sectors with Erase Suspend capability. - Automatically program and verify data at specified address • Erase suspend/Erase Resume - Suspends an erase operation to read data from, or program data to, another sector that is not being erased, then resumes the erase. Status Reply - Data polling & Toggle bit for detection of program and erase cycle completion. Sector protect/unprotect for 5V only system or 5V/ 12V system. Sector protection - Hardware method to disable any combination of sectors from program or erase operations 100,000 minimum erase/program cycles Latch-up protected to 100mA from -1V to VCC+1V Low VCC write inhibit is equal to or less than 3.2V Package type: - 32-pin PLCC, TSOP or PDIP Compatibility with JEDEC standard - Pinout and software compatible with single-power supply Flash 20 years data retention
•
• •
• • • • •
•
GENERAL DESCRIPTION
The MX29F040 is a 4-mega bit Flash memory organized as 512K bytes of 8 bits. MXIC's Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. The MX29F040 is packaged in 32-pin PLCC, TSOP, PDIP. It is designed to be reprogrammed and erased in system or in standard EPROM programmers. The standard MX29F040 offers access time as fast as 55ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the MX29F040 has separate chip enable (CE) and output enable (OE ) controls. MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX29F040 uses a command register to manage this functionality. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility. MXIC Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The MXIC cell is designed to optimize the erase and program mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The MX29F040 uses a 5.0V±10% VCC supply to perform the High Reliability Erase and auto Program/Erase algorithms. The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC + 1V.
P/N:PM0538
REV. 1.6, AUG. 08, 2001
1
MX29F040
PIN CONFIGURATIONS
32 PDIP
A18 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC WE A17 A14 A13 A8 A9 A11 OE A10 CE Q7 Q6 Q5 Q4 Q3
32 PLCC
VCC A12 A15 A16 A18 A17 30 29 WE
A7 A6 A5 A4 A3 A2 A1 A0 Q0
5
4
1
32
A14 A13 A8 A9
MX29F040
9
MX29F040
25
A11 OE A10 CE
13 14 Q1 Q2 GND
17 Q3 Q4 Q5
21 20 Q6
Q7
32 TSOP (Standard Type) (8mm x 20mm)
A11 A9 A8 A13 A14 A17 WE VCC A18 A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE Q7 Q6 Q5 Q4 Q3 GND Q2 Q1 Q0 A0 A1 A2 A3
MX29F040
PIN DESCRIPTION
SYMBOL A0~A18 Q0~Q7 CE WE OE GND VCC PIN NAME Address Input Data Input/Output Chip Enable Input Write Enable Input Output Enable Input Ground Pin +5.0V single power supply
SECTOR STRUCTURE
MX29F040 SECTOR ADDRESS TABLE Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 A18 0 0 0 0 1 1 1 1 A17 0 0 1 1 0 0 1 1 A16 0 1 0 1 0 1 0 1 Address Range 00000h-0FFFFh 10000h-1FFFFh 20000h-2FFFFh 30000h-3FFFFh 40000h-4FFFFh 50000h-5FFFFh 60000h-6FFFFh 70000h-7FFFFh
Note:All sectors are 64 Kbytes in size.
P/N:PM0538
REV. 1.6, AUG. 08, 2001
2
MX29F040
BLOCK DIAGRAM
WRITE CE OE WE CONTROL INPUT LOGIC HIGH VOLTAGE MACHINE (WSM) PROGRAM/ERASE STATE
X-DECODER
MX29F040 FLASH ARRAY ARRAY
STATE REGISTER
ADDRESS LATCH A0-A18 AND BUFFER
SENSE AMPLIFIER
Y-DECODER
Y-PASS GATE
SOURCE HV COMMAND DATA DECODER
PGM DATA HV COMMAND DATA LATCH
PROGRAM DATA LATCH
Q0-Q7
I/O BUFFER
P/N:PM0538
REV. 1.6, AUG. 08, 2001
3
MX29F040
AUTOMATIC PROGRAMMING
The MX29F040 is byte programmable using the Automatic Programming algorithm. The Automatic Programming algorithm makes the external system do not need to have time out sequence nor to verify the data programmed. The typical chip programming time at room temperature of the MX29F040 is less than 4 seconds.
AUTOMATIC ERASE ALGORITHM
MXIC's Automatic Erase algorithm requires the user to write commands to the command register .