Document
EN29F002 / EN29F002N
EN29F002 / EN29F002N 2 Megabit (256K x 8-bit) Flash Memory
FEATURES
• 5.0V ± 10% for both read/write operation • Read Access Time - 45ns, 55ns, 70ns, and 90ns • Fast Read Access Time - 70ns with Cload = 100pF - 45ns, 55ns with Cload = 30pF • Sector Architecture: One 16K byte Boot Sector, Two 8K byte Parameter Sectors, one 32K byte and three 64K byte main Sectors • Boot Block Top/Bottom Programming Architecture • High performance program/erase speed Byte program time: 10µs typical Sector erase time: 500ms typical Chip erase time: 3.5s typical • JEDEC standard DATA polling and toggle bits feature • Hardware RESET Pin (n/a for EN29F002N) • Single Sector and Chip Erase • Sector Protection / Temporary Sector Unprotect ( RESET = VID) • Sector Unprotect Mode • Embedded Erase and Program Algorithms • Erase Suspend / Resume modes: Read and program another sector during Erase Suspend Mode • 0.4 µm double-metal double-poly triple-well CMOS Flash Technology • Low Vcc write inhibit < 3.2V • 100K endurance cycle • Package Options - 32-pin PDIP - 32-pin PLCC - 32-pin TSOP (Type 1) • Commercial and Industrial Temperature Ranges
• Low Standby Current - 1µA CMOS standby current-typical - 1mA TTL standby current • Low Power Active Current - 30mA active read current - 30mA program / erase current • JEDEC Standard program and erase commands
GENERAL DESCRIPTION
The EN29F002 / EN29F002N is a 2-Megabit, electrically erasable, read/write non-volatile flash memory. Organized into 256K words with 8 bits per word, the 2M of memory is arranged in seven sectors (with top/bottom configuration), including one 16K Byte Boot Sector, two 8K Byte Parameter sectors, and four main sectors (one 32K Byte and three 64K Byte). Any byte can be programmed typically at 10µs. The EN29F002 / EN29F002N features 5.0V voltage read and write operation. The access times are as fast as 45ns to eliminate the need for WAIT states in high-performance microprocessor systems.
The EN29F002 / EN29F002N has separate Output Enable ( OE ), Chip Enable ( CE ), and Write Enable ( W E ) controls which eliminate bus contention issues. This device is designed to allow either single sector or full chip erase operation, where each sector can be individually protected against program/erase operations or temporarily unprotected to erase or program. The device can sustain a minimum of 100K program/erase cycles on each sector.
4800 Great America Parkway, Suite 202 1 Santa Clara, CA 95054 Rev. C, Issue Date: 2001/07/05
Tel: 408-235-8680 Fax: 408-235-8685
EN29F002 / EN29F002N
TABLE 1. PIN DESCRIPTION
Pin Name A0-A17 DQ0-DQ7 Function Addresses Data Input/Outputs Chip Enable Output Enable Write Enable Hardware Reset Sector Unprotect Supply Voltage (5V ± 10% ) Ground
CE OE WE RESET
NC on EN29F002N
FIGURE 1. LOGIC DIAGRAM
Vcc
18 A0 - A17 EN29F002T/B
8 DQ0 - DQ7
CE OE
WE
RESET
(n/a for EN29F002N)
Vcc Vss
Vss
TABLE 2. BLOCK ARCHITECTURE
TOP BOOT BLOCK
SECTOR
6 5 4 3 2 1 0
BOTTOM BOOT BLOCK
ADDRESSES
30000h - 3FFFFh 20000h - 2FFFFh 10000h - 1FFFFh 08000h - 0FFFFh 06000h - 07FFFh 04000h - 05FFFh 00000h - 03FFFh SIZE (Kbytes) 64 64 64 32 8 8 16
ADDRESSES
3C000h - 3FFFFh 3A000h - 3BFFFh 38000h - 39FFFh 30000h - 37FFFh 20000h - 2FFFFh 10000h - 1FFFFh 00000h - 0FFFFh
SIZE (Kbytes) 16 8 8 32 64 64 64
4800 Great America Parkway, Suite 202 2 Santa Clara, CA 95054 Rev. C, Issue Date: 2001/07/05
Tel: 408-235-8680 Fax: 408-235-8685
EN29F002 / EN29F002N
BLOCK DIAGRAM
Vcc Vss RESET
N/A on EN29F002N
Block Protect Switches
DQ0-DQ7
Erase Voltage Generator State Control Program Voltage Generator Chip Enable Output Enable Logic
STB
Input/Output Buffers
WE
Command Register CE OE
Data Latch
Y-Decoder
STB
Y-Gating
Vcc Detector
Timer
Address Latch
X-Decoder
Cell Matrix
A0-A17
4800 Great America Parkway, Suite 202 3 Santa Clara, CA 95054 Rev. C, Issue Date: 2001/07/05
Tel: 408-235-8680 Fax: 408-235-8685
EN29F002 / EN29F002N
FIGURE 2. PDIP
PDIP Top View
N/A for EN29F002N
VPP RESET A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC PGM WE NC A17 A14 A13 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3
FIGURE 3. TSOP
A17
WE N/A for EN29F002N RESET
EN29F002
FIGURE 4. PLCC
PLCC Top View
A12 A16 VCC A17 A12 A16 VCC NC A17 A15 A15 RESET VPP WE PGM
4 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 3 2 1 32 31 30 29 28 27 26 25 24 23 22 21 A14 A13 A8 A9 A11 OE A10 CE DQ7
RESET is not applicable for EN29F002N
DQ2 DQ3 DQ5 DQ1 VSS DQ4 DQ6
4800 Great America Parkway, Suite 202 4 Santa Clara, CA 95054 Rev. C, Issue Date: 2001/07/05
Tel: 408-235-8680 Fax: 408-235-8685
EN29F002 / EN29F002N
TABLE 3. OPERATING MODES 2M FLASH USER MODE TABLE
CE
USER MODE RESET
(n/a for EN29F002N)
WE
OE
RESET
A9
X X A9 A9 VID VID VID VID VID A9 X
A8
X X A8 A8 L/H L/H X X X A8 X
A6
X X A6 A6 L L L L H A6 X
A1
X X A1 A1 L L H X H A1 X
A0
X X A0 A0 L H L X L A0 X
Ax/.