IBM25PPC440GX

Preliminary PowerPC 440GX Embedded Processor Data Sheet Features PowerPC® 440 processor core operating up to 800MHz with 32KB I- and D-caches (with parity checking) On-chip 256KB SRAM configurable as L2 Code store or Ethernet Packet store memory Selectable processor:bus clock ratios (Refer to the Clocking chapter in the PPC440GX Embedded Processor User’s Manual for details) Double Data Rate (DDR) Synchronous DRAM (SDRAM) interface operating up to 166MHz External Peripheral Bus (32 bits) for up to eight devices with external mastering DMA support for external peripherals, internal UART and memory PCI-X V1.0a interface (32 or 64 bits, up to 133MHz) with support for conventional PCI V2.3 Two Ethernet 10/100/1000Mbps half- or fullduplex interfaces. Operational modes supported are SMII, GMII, RGMII, TBI and RTBI. TCP/IP Acceleration Hardware (TAH) provided for 10/100/1000 Mbps ports that performs checksum processing, TCP segmentation, and includes support for jumbo frames Two Ethernet 10/100Mbps half- or full-duplex interfaces. Operational modes supported are MII, RMII, and SMII. Programmable Interrupt Controller supports interrupts from a variety of sources. I2O Messaging unit for message transfer between the CPU and PCI-X Programmable General Purpose Timers (GPT) Two serial ports (16750 compatible UART) Two IIC interfaces General Purpose I/O (GPIO) interface available JTAG interface for board level testing Processor can boot from PCI memory ...