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IMIC9716J Dataheets PDF



Part Number IMIC9716J
Manufacturers International
Logo International
Description (C9716) 100 Mhz Clock General
Datasheet IMIC9716J DatasheetIMIC9716J Datasheet (PDF)

C9716J 100 MHz Clock Generator with SSCG and Power Management for Mobile Application Preliminary Product Features • • • • • • • • • • Supplies: 2 Ref clocks 2 Host (CPU) clocks 1 free running and 5 PCI Clocks 1 48MHz fixed clock 1 48 or 24 MHz fixed clock Separate supply pins for mixed (3.3/2.5V) voltage application. 100 or 66 MHz CPU clock operation -1.5% Spread Spectrum modulation for reducing EMI Rich Power Management Functions. 28-pin SSOP & TSSOP packages for minimum board space. Frequency.

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C9716J 100 MHz Clock Generator with SSCG and Power Management for Mobile Application Preliminary Product Features • • • • • • • • • • Supplies: 2 Ref clocks 2 Host (CPU) clocks 1 free running and 5 PCI Clocks 1 48MHz fixed clock 1 48 or 24 MHz fixed clock Separate supply pins for mixed (3.3/2.5V) voltage application. 100 or 66 MHz CPU clock operation -1.5% Spread Spectrum modulation for reducing EMI Rich Power Management Functions. 28-pin SSOP & TSSOP packages for minimum board space. Frequency Table SEL 100/66# 0 1 CPU Clock 66.66 MHz 100.00 MHz PCI Clock 33.33 MHz 33.33 MHz Block Diagram SEL48# Pin Configuration REF2 VDDR XIN XOUT OSC SS# REF1 SEL48# PLL 48-24M 48-24M/TS# VDDC SEL100/66# CS# PD# PS# SS# PLL CPU (1,2) PCI_F VDDP VSS XIN XOUT PCI_F PCI1 PCI2 VSS VDDP PCI3 PCI4 PCI5 VDDF 48M 48-24/TS# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDDR REF/SEL48# REF1/SS# VDDC CPU1 CPU2 VSS VSS PS# VDD CS# PD# SEL100/66# VSS PCI (1:3) INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571 Rev. 1.0 4/28/2000 Page 1 of 12 C9716J 100 MHz Clock Generator with SSCG and Power Management for Mobile Application Preliminary Pin Description PIN No. 2 Pin Name XIN PWR VDD I/O I TYPE XTAL4 Description On-chip reference oscillator input pin. Requires either an external parallel resonant crystal (nominally 14.318 MHz) or externally generated reference signal O-chip reference oscillator output pin. Drives an external parallel resonant crystal (14.318 MHz) when an externally generated reference signal is used. 3.3 volt power supply for core logic. Clock outputs. CPU frequency table specified on page 1. Powers down device when LOW When signal is LOW, stops CPU clocks in low state. Frequency select input pins. See frequency select table on page 1. NO INTERNAL PULLUP RESISTOR IS PROVIDED BY DEVICE 2.5V power for CPU and Host clock outputs. Free running PCI clock 3.3V. Does not stop when PS# is at a logic LOW level PCI output clocks. See frequency table of page 1. When signal is LOW, stops all PCI clocks in low state. 3.3 Volt power supply pins for free running PCI clock output buffer. Fixed 48 MHz clock. Power up selectable 48 or 24 MHz clock. If strapped LOW at powerup causes the devices outputs to be tri-stated until the next power up sequence occurs. At power up this pin determines if the device’s spread spectrum modulation feature is enabled or disabled. After power up this pin becomes a reference clock output. A 0 (logic low) enables SSCG and a 1 (logic high) disables SSCG. At power up this pin determine the frequency of the clock at pin 14. If it is LOW, the clock will be 48 MHz, if HIGH the clock will be 24 MHz. After power up this pin will become a reference clock output. Power for fixed clock output buffer. Ground pins for device. Power for Reference Oscillator output buffer. 3 XOUT VDD O XTAL4 19 23, 24 17 18 16 VDD CPU (1,2) PD# CS# SEL100.


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