TC58NS512ADC

TC58NS512ADC TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 2 TM 512-MBIT (64M × 8 BITS) CMOS NAND E PROM (64M BYTE SmartMedia DESCRIPTION ) The TC58NS512A is a single 3.3-V 512-Mbit (553,648,128) bit NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as 528 bytes × 32 pages × 4096 blocks. The device has a 528-byte static register which allows program and read data to be transferred between the register and the memory cell array in 528-byte increments. The Erase operation is implemented in a single block unit (16 Kbytes + 512 bytes: 528 bytes × 32 pages). The TC58NS512A is a serial-type memory device which utilizes the I/O pins for both address and data input/output as well as for command inputs. The Erase and Program operations are automatically executed. The TC58NS512DC is a SmartMediaTM with ID and each device has 128 bit unique ID number embedded in the device. This unique ID number is applicable to image files, music files, electronic books, and so on where copyright protection is required. The data stored in the TC58NS512ADC needs to comply with the data format standardized by the SSFDC Forum in order to maintain compatibility with other SmartMediaTM systems. FEATURES Organization Memory cell allay 528 × 128K × 8 Register 528 × 8 Page size 528 bytes Block size (16K + 512) bytes Modes Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Mode control Serial input/output, Command control Complies with th...