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UPD4516161D Dataheets PDF



Part Number UPD4516161D
Manufacturers Elpida
Logo Elpida
Description 16M Bit Synchronous DRAM
Datasheet UPD4516161D DatasheetUPD4516161D Datasheet (PDF)

DATA SHEET MOS INTEGRATED CIRCUIT µPD4516161D 16M-bit Synchronous DRAM 2-banks, LVTTL Description The µPD4516161D is high-speed 16,777,216-bit synchronous dynamic random-access memory, organized as 524,288 words × 16 bits × 2 banks respectively. The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture. All inputs and outputs are synchronized with the positive edge of the clock. The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL). This product is pa.

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DATA SHEET MOS INTEGRATED CIRCUIT µPD4516161D 16M-bit Synchronous DRAM 2-banks, LVTTL Description The µPD4516161D is high-speed 16,777,216-bit synchronous dynamic random-access memory, organized as 524,288 words × 16 bits × 2 banks respectively. The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture. All inputs and outputs are synchronized with the positive edge of the clock. The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL). This product is packaged in 50-pin TSOP (II). Features • Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge • Pulsed interface • Possible to assert random column address in every cycle • Dual internal banks controlled by A11 • Byte control by LDQM and UDQM • Programmable Wrap sequence: Sequential / Interleave • Programmable burst length: 1, 2, 4, 8 and full page • /CAS latency: 3 • CBR (Auto) refresh and self refresh • ×16 organization • Single 3.3 V ± 0.3 V power supply • LVTTL compatible • 2,048 refresh cycles / 32 ms • Burst termination by Burst stop command and Precharge command Ordering Information Part number Organization (word × bit × bank) 512K × 16 × 2 Clock frequency MHz (MAX.) 143 133 125 100 Package 50-pin PLASTIC TSOP (II) (10.16mm(400)) µPD4516161DG5-A70-9NF µPD4516161DG5-A75-9NF µPD4516161DG5-A80-9NF µPD4516161DG5-A10-9NF The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for availability and additional information. Document No. E0143N10 (Ver.1.0) (Previous No. M14888EJ2V0DS00) Date Published May 2001 CP (K) Printed in Japan Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd. µPD4516161D Part Number µPD4516161DG5 - A80 NEC Memory Synchronous DRAM Memory density 16 : 16M bits Organization 16 : x16 Minimum cycle time 70 75 80 10 : 7 ns (143 MHz) : 7.5 ns (133 MHz) : 8 ns (125 MHz) : 10 ns (100 MHz) Number of banks and Interface 1 : 2 banks, LVTTL Low voltage A : 3.3 V ± 0.3 V Version Package G5 : TSOP (II) 2 Data Sheet E0143N10 µPD4516161D Pin Configuration /xxx indicates active low signal. [ µPD4516161DG5 ] 50-pin PLASTIC TSOP (II) (10.16mm (400)) 512K words × 16 bits × 2 banks VCC DQ0 DQ1 VSSQ DQ2 DQ3 VCCQ DQ4 DQ5 VSSQ DQ6 DQ7 VCCQ LDQM /WE /CAS /RAS /CS A11 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 Vss DQ15 DQ14 VssQ DQ13 DQ12 VccQ DQ11 DQ10 VssQ DQ9 DQ8 VccQ NC UDQM CLK CKE NC A9 A8 A7 A6 A5 A4 Vss A0 to A11 CLK CKE /CS /RAS /CAS /WE LDQM UDQM VCC VSS VCCQ VSSQ NC Note : Address inputs : Clock input : Clock enable : Chip select : Row address strobe : Column address strobe : Write enable : Lower DQ mask enable : Upper DQ mask enable : Supply voltage : Ground : Supply voltage for DQ : Ground for DQ : No connection Note A0 to A10 : Row address inputs A0 to A7 : Column address inputs A11 : Bank select DQ0 to DQ15 : Data inputs / outputs Data Sheet E0143N10 3 µPD4516161D Block Diagram CLK CKE Clock Generator Bank B Address Mode Register Row Decoder Row Address Buffer & Refresh Counter Bank A Sense Amplifier Command Decoder Control Logic /CS /RAS /CAS /WE Data Control Circuit Input & Output Buffer Latch Circuit Column Address Buffer & Burst Counter Column Decoder & Latch Circuit DQM DQ 4 Data Sheet E0143N10 µPD4516161D CONTENTS 1. 2. 3. 4. Input / Output Pin Function............................................................................................................... 7 Commands.......................................................................................................................................... 8 Simplified State Diagram ................................................................................................................ 11 Truth Table ....................................................................................................................................... 12 4.1 Command Truth Table ............................................................................................................................. 12 4.2 DQM Truth Table ...................................................................................................................................... 12 4.3 CKE Truth Table ....................................................................................................................................... 12 4.4 Operative Command Table ..................................................................................................................... 13 4.5 Command Truth Table for CKE .............................................................................................................. 16 4.6 Command Truth Table for Two Banks Operati.


UPD4516161 UPD4516161D CY120


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