HT6560B

HT — 6560B VL_BUS ENHANCED IDE CONTROLLER DEC.07.1994 PAGE: 1 A. General Description — HT–6560B is a VL_Bus Enhanced IDE Controller which provides a control logic and data path between 486, 386 VL_Bus and IDE drives. The HT–6560B is fully compatible with the ANSI ATA revision 4a specification for IDE hard disk operation and VESA VL_Bus revision 1.0 specification for local bus PC drives. The HT–6560B is a high performance and fully design for IDE application. At the host CPU interface, HT–6560B provides a posted write and pre-fetched read fully 32 bits data path. It can operate up to 50 MHz and zero wait-state cycle. Double word read and write operations are provided. It also allows concurrent IDE and CPU memory operations to maximize system performance. Flexible IDE drive interface timing selection. Power on reset latch the adequate IDE active and recovery time into configuration register. HT–6560B also allows you to detect IDE performance and change the configuration register by software program. B. Features — Pin-to-pin backward compatible with HT–6560A VL_Bus IDE controller IDE interface to 486 and 386 DX/SX local bus VESA VL_Bus rev 1.0 compatible Connects directly to VL_Bus and IDE interface, no extra TTL needed Supports 16 bits and 32 bits data transfer Supports pipeline pre-fetched data reads and posted writes for concurrent disk and host operations Supports 4 layer R/W FIFO (32 bits × 4) Supports two IDE channels, up to 4 IDE drivers S...