SP8402KGMPES

SP8402 Very Low Phase Noise Divider by 2N DS3738 - 2.1 March 1994 The SP8402 is a very low phase noise divider which divides by powers of two. The S0, S1, S2 data inputs select the division ratio in the range 21 to 28. Special circuits techniques have been used to reduce the phase noise considerably below that produced by standard dividers. The data inputs are CMOS or TTL compatible. The SP8402 is packaged in a 28 pin plastic SO package to be compatible with the SP8400 and SP8401 devices. N/C N/C N/C VCC +5V GND CLOCK INPUT CLOCK INPUT CLOCK INPUT CLOCK INPUT GND VCC +5V VCC +5V N/C S0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 N/C N/C N/C N/C N/C N/C N/C OUTPUT OUTPUT N/C VCC +5V N/C S2 S1 FEATURES s Very low Phase Noise (Typically -155 to 160dBc/Hz at 1kHz offset) s Supply Voltage 5V ABSOLUTE MAXIMUM RATINGS Supply Voltage Output Current Storage Temperature Range Maximum Clock Input Voltage 6.5V 20mA -55°C to +125°C 2.5V p-p MP28 Fig.1 Pin connections - top view ORDERING INFORMATION SP8402 KG MPES (Commercial Grade) 0 –10 –20 –30 –40 –50 (f) (dBc/Hz) –3dB –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 10 100 1k Frequency (Hz) 10k 100k Fig.2 Typical single sideband phase noise measured at 768MHz SP8400 ELECTRICAL CHARACTERISTICS Guaranteed over: Supply voltage VCC = +4.75V to +5.25V Temperature Tamb = -10°C to +75°C Tested at +4.75V and +5.25V at Tamb = +25°C Characteristic Pin Min. 4, 11, 12, 18 20, 21 7, 8 82 320 Va...