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ST70136 Dataheets PDF



Part Number ST70136
Manufacturers ST Microelectronics
Logo ST Microelectronics
Description CPE ADSL ANALOG FRONT END
Datasheet ST70136 DatasheetST70136 Datasheet (PDF)

ST70136 CPE ADSL ANALOG FRONT END s WIDE TRANSMIT AND RECEIVE DYNAMIC s s s s s s s s s s s s RANGE TO REDUCE EXTERNAL FILTERING REQUIREMENTS RECEIVE PROGRAMMABLE GAIN: 0 TO 31dB GAIN IN 1dB STEPS RECEIVE PROGRAMMABLE ATTENUATOR 0,-4dB, -8dB, -12dB 12-BIT A/D CONVERTER IN RECEIVE PATH TRANSMIT PROGRAMMABLE GAIN: 0 TO -15dB IN 1dB STEPS 14-BIT D/A CONVERTER IN TRANSMIT PATH LOW POWER MODE: 10mW IN LISTENING MODE, 250µW IN POWER DOWN TONE DETECTOR: ACTIVITY DETECTION FOR WAKE-UP FUNCTION 64-PIN TQ.

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ST70136 CPE ADSL ANALOG FRONT END s WIDE TRANSMIT AND RECEIVE DYNAMIC s s s s s s s s s s s s RANGE TO REDUCE EXTERNAL FILTERING REQUIREMENTS RECEIVE PROGRAMMABLE GAIN: 0 TO 31dB GAIN IN 1dB STEPS RECEIVE PROGRAMMABLE ATTENUATOR 0,-4dB, -8dB, -12dB 12-BIT A/D CONVERTER IN RECEIVE PATH TRANSMIT PROGRAMMABLE GAIN: 0 TO -15dB IN 1dB STEPS 14-BIT D/A CONVERTER IN TRANSMIT PATH LOW POWER MODE: 10mW IN LISTENING MODE, 250µW IN POWER DOWN TONE DETECTOR: ACTIVITY DETECTION FOR WAKE-UP FUNCTION 64-PIN TQFP PACKAGE 64-PIN LFBGA PACKAGE 0.50µm, 5V BICMOS TECHNOLOGY 3.3V DIGITAL INTERFACE 5V ANALOG INTERFACE The AFE receive path contains a programmable gain amplifier (RxPGA), a low pass anti-aliasing filter, and a 12-bit A/D converter. The RxPGA is digitally programmable from 0 to 31dB in 1dB steps. The AFE transmit path consists of a 14-bit D/A converter, followed by a programmable gain amplifier (TxPGA). The transmit gain is programmable from 0 to -15dB in 1dB steps. TQFP64 Full Plastic (10 x 10 x 1.40 mm) ORDER CODE: ST70136G INTRODUCTION The ST70136 ADSL Analog Front End (AFE) chip implements the analog transceiver functions required in a Customer Premise ADSL modem. It connects the digital modem chip with the loop driver and hybrid balance circuits. The AFE has been designed with high dynamic range in order to greatly reduce the external filtering requirements at the front end. The AFE chip and its companion digital chip along with a loop driver, implement the complete G.992.2 and G.992.1 DMT modem solution. Figure 1 : Overall Application Block Diagram Software for Control xDSL LFBGA64 (8 x 8 x 1.7 mm) ORDER CODE: ST70136B PC PCI or USB PCI or USB LINE DMT xDSL AFE LOOP DRIVER HYBRID ST70137 ST70136 TS612/TS652 September 2001 1/24 ST70136 ST70136 Pinout VDDOSC VCOCAP VCXOUT VSSOSC VSSESD VDDA6 VDDA5 50 48 VSDA VDDA4 PGAP TXIN TXP TXN TXIP PGAN VSSA4 VSSA3 V290DA V125AD V250AD 35 34 33 V375AD VSBIAS V3P75V 47 46 45 44 43 42 41 49 VSSA5 40 39 38 37 36 32 IREF50U 31 VDDA3 XTALO VSSA6 XTALI IVCO TON TOP GC0 52 51 29 RXN 30 VDDA1 64 CTRLIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 SUSPEND VDDA2 VSSA2 VSAD VDD PWD NRESET VSSA1 TEST VSRX RXP VSS 18 19 20 21 22 23 24 25 26 27 28 CTRLOUT R/W VDDIO CLKWD CLKM ACTD RX3 RX2 RX1 RX0 VSSIO TX3 TX2 TX1 TX0 63 62 61 60 59 58 57 56 55 54 53 ST70136G 2/24 GC1 ST70136 1 - PIN LIST The following list gives the different PIN Types: AI Analog Input AIO Analog Input/Output AO Analog Ouptut DI Digital Input DIO Digital Input/Output Table 1 : Pin Assignment Pins Name TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 LFBGA B2 C3 C2 B1 A1 C1 D2 D1 E2 E1 F2 G2 F1 G1 H2 H1 E3 G3 E4 H3 F3 G4 F4 H4 G5 E5 H5 H6 CTRLIN CTRLOUT R/NW* VDDIO CLKWD CLKM ACTD RX3 RX2 RX1 RX0 VSSIO TX3 TX2 TX1 TX0 VSS TEST NRESET* VDD PWD SUSPEND VDDA2 VSSA2 VSAD VSRX VSSA1 RXP DI DO DI VDDD DO DO O DO DO DO DO VDDD DI DI DI DI VSSD DI DI VSSD DI DI VDDA VSSA VSSA VSSA VSSA AI Digital input for control interface Digital output for control interface Selection of read or write mode for control interface I/O buffer supply voltage 8.832MHz output clock. Used to synchronize RX/TX word data exchange, and master clock of register control interface 35.328MHz Master Clock. Xtal buffer Tone Detector Activation Received data output Received data output Received data output Received data output I/O buffer ground voltage Transmit data input Transmit data input Transmit data input Transmit data input Core digital ground Test mode is activated with TEST=1. Must be tied to ground in normal mode Reset input. All digital circuitry is well defined after a negative pulse on this input Core digital supply (3.3V) Power Down pin Suspend Mode pin ADC supply voltage (5V) ADC ground voltage Substrate voltage for RX-AD path (Must be connected to VSSAx) Substrate voltage for RXPGA path (Must be connected to VSSAx) RXPGA ground voltage Positive Analog Receive input Type Description DO VDDA VDDD VSSA VSSD Digital Output Analog Power Supply Digital Power Supply Analog Ground Digital Ground 3/24 ST70136 Table 1 : Pin Assignment (continued) Pins Name TQFP 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 LFBGA H7 G6 F5 H8 G8 G7 F7 F8 F6 E7 E8 E6 D6 D8 D7 C7 C8 B7 B8 A8 A7 C6 A6 B6 D5 C5 B5 D4 A5 C4 A4 B4 D3 A3 B3 A2 RXN VDDA1 VDDA3 IREF50U V3P75V VSBIAS V375AD V250AD V125AD V290DA VSSA3 VSSA4 PGAN TXIP TXN TXP TXIN PGAP VDDA4 VSDA VSSA5 VDDA5 GC1 GC0 VDDA6 TON TOP VCXOUT IVCO VCOCAP VSSA6 VSSESD VSSOSC XTALI XTALO VDDOSC AI VDDA VDDA AI AO VSSA AO AO AO AO VSSA VSSA AO AI AO AO AI AO VDDA VSSA VSSA VDDA DO DO VDDA AI AI AIO AIO AO VSSA VSSD VSSD DI DO VDDD Negative Analog Receive input RXPGA voltage supply (5v) Bias and References voltage supply (5v) External resistor for bias current 50kΩ 3.75v output from bandgap; 0.22µF decoupling Substrate voltage for biasing & reference cell (Must be connected to VSSAx) 3.75 volt ref.


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