Document
EMBEDDED ULTRA-LOW POWER Intel486™ GX PROCESSOR
s Ultra-Low Power Member of the Intel486™ s 16-Bit External Data Bus
Processor Family s — 32-Bit RISC Technology Core s — 8-Kbyte Write-Through Cache s — Four Internal Write Buffers — Burst Bus Cycles s — Data Bus Parity Generation and s Checking — Intel System Management Mode (SMM) — Boundary Scan (JTAG)
176-Lead Thin Quad Flat Pack (TQFP) Separate Voltage Supply for Core Circuitry Fast Core-Clock Restart Auto Clock Freeze Ideal for Embedded Battery-Operated and Hand-Held Applications
64-Bit Interunit Transfer Bus
32-Bit Data Bus 32-Bit Data Bus Linear Address
32 32 32
PCD PWT
Core Clock
Clock Control
CLK Input
Barrel Shifter Register File ALU
Base/ Index Bus 32
Segmentation Unit Descriptor Registers Limit and Attribute PLA
2
Bus Interface
Paging Unit
Cache Unit
20 Physical Address 8 Kbyte Cache
32
Address Drivers Write Buffers 4 x 32 Data Bus 32 Transceivers
A31-A2 BE3#- BE0#
Translation Lookaside Buffer
32
D15-D0
128 Displacement Bus 32 MicroInstruction 32-Byte Code Queue 2x16 Bytes Prefetcher
Bus Control
Request Sequencer Burst Bus Control
ADS# W/R# D/C# M/IO# PCD PWT RDY# LOCK# PLOCK# BOFF# A20M# BREQ HOLD HLDA RESET SRESET INTR NMI SMI# SMIACT# STPCLK#
Control & Protection Test Unit
Code Stream Instruction Decode Decoded Instruction Path 24
BRDY# BLAST#
Control ROM
Parity Generation and Control Cache Control Boundary Scan Control
DP1-DP0, PCHK#
KEN# FLUSH# AHOLD EADS#
TCK TMS TDI TD0
A5851-01
Figure 1. Embedded Ultra-Low Power Intel486™ GX Processor Block Diagram © INTEL CORPORATION, 1997 December 1997 Order Number: 272755-002
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Contents
Embedded Ultra-Low Power Intel486™ GX Processor
1.0 INTRODUCTION ........................................................................................................................................ 1 1.1 Features ............................................................................................................................................. 1 1.2 Family Members ................................................................................................................................. 3 2.0 HOW TO USE THIS DOCUMENT ............................................................................................................. 3 3.0 PIN DESCRIPTIONS ................................................................................................................................. 3 3.1 Pin Assignments ................................................................................................................................. 3 3.2 Pin Quick Reference ........................................................................................................................... 7 4.0 ARCHITECTURAL AND FUNCTIONAL OVERVIEW ............................................................................. 15 4.1 Separate Supply Voltages ................................................................................................................ 15 4.2 Fast Clock Restart ............................................................................................................................ 16 4.3 Level-Keeper Circuits ..........................................